Two-tier defect scan management
US-2024402922-A1 · Dec 5, 2024 · US
Error detection and correction circuitry
US8984367B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8984367-B2 |
| Application number | US-201113035826-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 25, 2011 |
| Priority date | Feb 25, 2011 |
| Publication date | Mar 17, 2015 |
| Grant date | Mar 17, 2015 |
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Abstract
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Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for operating an integrated circuit that includes a memory array comprising a plurality of memory elements and associated address lines and data lines, wherein a first set of memory elements in the memory array is coupled to a first address line and a second set of memory elements in the memory array is coupled to a second address line that is different from the first address line, the method comprising: detecting errors in the first and second sets…
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Classifications
Physics · mapped topic
- G11C29/52Primary
Physics · mapped topic
Electricity · mapped topic
- G06F11/1076Primary
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8984367B2 cover?
- Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit proc…
- Who is the assignee on this patent?
- Ekas Paul B, Lewis David, Altera Corp
- What technology area does this patent fall under?
- Primary CPC classification G11C29/52. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).