Semiconductor device including trench structure and manufacturing method

Patent metadata

Field	Value
Publication number	US-11276754-B2
Application number	US-202016811293-A
Country	US
Kind code	B2
Filing date	Mar 6, 2020
Priority date	Mar 7, 2019
Publication date	Mar 15, 2022
Grant date	Mar 15, 2022

Abstract

An embodiment of a semiconductor device includes a silicon carbide semiconductor body including source and body regions of opposite conductivity types. A trench structure extends from a first surface into the silicon carbide semiconductor body along a vertical direction, and includes a gate electrode and a gate dielectric. A contact is electrically connected to the source region at the first surface. The source region includes a first source sub-region directly adjoining the contact at a source contact area of the first surface, a second source sub-region, and a third source sub-region. The second sub-region is arranged between the first and third sub-regions along the vertical direction. A doping concentration profile along the vertical direction of the source region includes a doping concentration minimum in the second sub-region and a doping concentration maximum in the third sub-region. Each of the second and third sub-regions overlaps with the source contact area.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a silicon carbide semiconductor body comprising a source region of a first conductivity type and a body region of a second conductivity type;
a trench structure extending from a first surface of the silicon carbide semiconductor body into the silicon carbide semiconductor body along a vertical direction, the trench structure comprising a gate electrode and a gate dielectric; and
a contact electrically connected to the source region at the first surface,
wherein the source region comprises a first source sub-region directly adjoining the contact at a source contact area of the first surface, a second source sub-region, and a third source sub-region, the second source sub-region being arranged between the first source sub-region and the third source sub-region along the vertical direction,
wherein a doping concentration profile along the vertical direction of the source region includes a doping concentration minimum in the second source sub-region and a doping concentration maximum in the third source sub-region,
wherein each of the second source sub-region and the third source sub-region overlaps with the source contact area.

2. The semiconductor device of claim 1 , wherein the gate electrode is directly opposed to each of the first source sub-region, the second source sub-region and the third source sub-region.

3. The semiconductor device of claim 1 , wherein the doping concentration profile along the vertical direction of the source region includes a doping concentration valley in the second source sub-region and a doping concentration peak in the third source sub-region.

4. The semiconductor device of claim 1 , wherein a lateral extent of the second source sub-region is defined between an interface to a sidewall of the trench structure and a pn junction to the body region, and wherein a doping concentration profile of the second source sub-region is constant along at least 80% of the lateral extent.

5. The semiconductor device of claim 1 , wherein the doping concentration minimum in the second source sub-region is in a range of at least 0.01% to at most 50% of the doping concentration maximum in the third source sub-region.

6. The semiconductor device of claim 1 , wherein a vertical extent of the second source sub-region is in a range of at least 30 nm to at most 300 nm.

7. The semiconductor device of claim 1 , wherein at least a part of the second source sub-region comprises dopants of the second conductivity type, and wherein the dopants of the second conductivity type partially compensate dopants of the first conductivity type in a range of at least 10% to at most 99.9%.

8. The semiconductor device of claim 1 , further comprising lattice defects in the second source sub-region, wherein the lattice defects reduce mobility of free charge carriers in the second source sub-region.

9. The semiconductor device of claim 1 , further comprising lattice defects in the second source sub-region, wherein the lattice defects reduce an effective n-type doping level in the second source sub-region.

10. A method of manufacturing a semiconductor device, the method comprising:
forming a source region of a first conductivity type and a body region of a second conductivity type in a silicon carbide semiconductor body;
forming a trench structure extending from a first surface of the silicon carbide semiconductor body into the silicon carbide semiconductor body along a vertical direction, the trench structure comprising a gate electrode and a gate dielectric; and
forming a contact electrically connected to the source region at the first surface,
wherein the source region comprises a first source sub-region directly adjoining the contact at a source contact area of the first surface, a second source sub-region, and a third source sub-region,
wherein the second source sub-region is arranged between the first source sub-region and the third source sub-region along the vertical direction,
wherein a doping concentration profile along the vertical direction of the source region includes a doping concentration minimum in the second source sub-region and a doping concentration maximum in the third source sub-region,
wherein each of the second source sub-region and the third source sub-region overlaps with the source contact area.

11. The method of claim 10 , wherein the first source sub-region, the second source sub-region and the third source sub-region are formed by ion implantation processes using a same ion implantation mask.

Assignees

• Infineon Technologies Ag

Inventors

• Basler Thomas
• Leendertz Caspar
• Schulze Hans-Joachim

Classifications

• H10P30/22

  using masks · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D30/668

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/01

  Manufacture or treatment · CPC title