Database lookup using a scannable code for part selection

Patent metadata

Field	Value
Publication number	US-11276098-B2
Application number	US-201715793332-A
Country	US
Kind code	B2
Filing date	Oct 25, 2017
Priority date	Oct 25, 2017
Publication date	Mar 15, 2022
Grant date	Mar 15, 2022

Abstract

Embodiments described herein include techniques for providing information regarding a hardware part using a scannable code so that a customer can make an informed decision when placing the hardware part in a larger computing system. A customer may purchase hardware parts that are categorized into a certain bin which has guaranteed range of power consumption or performance. The customer may over design the computing system to accommodate the worst parameter in the range (e.g., the minimum performance or the maximum power consumption) to ensure the timing or power specifications are not violated. Instead, the embodiments herein provide a scannable code on the hardware part which the customer can use to access a database which stores more granular information about the part. The customer can use the performance parameters to make better informed decisions to determine where to place the part in the computing system.

First claim

What is claimed is:

1. A method comprising:
scanning an identifying code using a scanning device, wherein the identifying code is disposed in a semiconductor package that includes an integrated circuit and scanning the identifying code comprises querying a database using a unique identifier, wherein the identifying code encodes the unique identifier and the unique identifier is associated with circuit-based identifier;
receiving different performance parameters corresponding to the integrated circuit from the querying of the database using the unique identifier;
determining whether the integrated circuit satisfies a plurality of different predefined operation selection rules corresponding to a first location in an assembled computing system using the different performance parameters; and
placing the semiconductor package in the first location on the assembled computing system.

2. The method of claim 1 , further comprising:
scanning a plurality of identifying codes, each of which are disposed in a respective semiconductor package that includes a respective integrated circuit; and
receiving respective performance parameters corresponding to the respective integrated circuits using identifier data retrieved from scanning the plurality of identifying codes.

3. The method of claim 2 , further comprising:
determining that the respective integrated circuits do not satisfy the plurality of different predefined operation selection rules corresponding to the first location in the assembled computing system using the respective performance parameters.

4. The method of claim 3 , further comprising:
storing the respective performance parameters in a data store in respective data entries corresponding to the respective semiconductor packages; and
determining, before determining that the respective integrated circuits do not satisfy the plurality of different predefined operation selection rules, whether the respective semiconductor packages are available for placement on the assembled computing system by querying the data store.

5. The method of claim 2 , further comprising:
evaluating the assembled computing system for additional packages that affect compatibility of the semiconductor package at the first location.

6. The method of claim 2 , further comprising:
determining an optimal integrated circuit to place at a second location of the assembled computing device by comparing the respective performance parameters with at least one predefined operation selection rule corresponding to the second location; and
placing the respective semiconductor package corresponding to the optimal integrated circuit at the second location.

7. The method of claim 1 , wherein a predefined operation selection rule of the plurality of different predefined operation selection rules defines at least one of a minimum performance value and a maximum power consumption that the integrated circuit must have to be placed at the first location.

8. The method of claim 1 , wherein the identifying code comprises at least one of a one-dimensional, two-dimensional, and three-dimensional bar code, wherein the different performance parameters are retrieved from a registration system maintained by a first entity that sold the semiconductor package
wherein retrieving the performance parameter from the registration system comprises:
transmitting authorization data to the registration system which uses the authorization data to determine whether a second entity requesting the performance parameter has permission to access the performance parameter.

9. The method of claim 1 , wherein the different performance parameters comprise at least one of maximum and minimum operational frequency ranges of the integrated circuit, average power requirements of the integrated circuit, minimum power requirements of the integrated circuit, a leakage current of the integrated circuit, a minimum voltage operational level of the integrated circuit, and life expectancy information of the integrated circuit.

10. A system, comprising:
a bar code scanner configured to scan an identifying code disposed in a semiconductor package that includes an integrated circuit;
a processor; and
a memory comprising an assembly application, wherein the assembly application, when executed by the processor performs an operation comprising:
querying a database using a unique identifier generated by the bar code scanner scanning the identifying code, wherein the identifying code encodes the unique identifier and the unique identifier is associated with circuit-based identifier;
receiving different performance parameter corresponding to the integrated circuit from the querying of the database using the unique identifier,
determining whether the integrated circuit satisfies a plurality of different predefined operation selection rules corresponding to a first location in an assembled computing system using the different performance parameters, wherein the plurality of different predefined operation selection rules indicates a maximum power consumption threshold and a minimum operational frequency threshold for the first location; and
instructing the semiconductor package to be placed in the first location on the assembled computing system.

11. The system of claim 10 , wherein the operation comprises:
receiving respective performance parameters corresponding to respective integrated circuits using identifier data retrieved from scanning a plurality of identifying codes, wherein each of the plurality of identifying codes is disposed in a respective semiconductor package that includes one of the respective integrated circuits,
wherein the respective performance parameters comprise at least one of maximum and minimum operational frequency ranges of the integrated circuits, average power requirements of the integrated circuits, minimum power requirements of the integrated circuits, a leakage current of the integrated circuits, a minimum voltage operational level of the integrated circuits, and life expectancy information of the integrated circuits.

12. The system of claim 11 , wherein the operation comprises:
determining that the respective integrated circuits do not satisfy the plurality of different predefined operation selection rules corresponding to the first location in the assembled computing system using the respective performance parameters.

13. The system of claim 11 , wherein the operation further comprises:
evaluating the assembled computing system for additional packages that affect compatibility of the semiconductor package at the first location.

14. The system of claim 11 , wherein the operation further comprising:
determining that the integrated circuit is a more optimal candidate for a second location of the assembled computing system by comparing the respective performance parameters with at least one predefined operation selection rule corresponding to the second location; and
placing the respective semiconductor package corresponding to the optimal integrated circuit at the second location.

15. The system of claim 10 , wherein a predefined operation selection rule of the plurality of different predefined operation selection rules defines at least one of a minimum performance value and a maximum power consumption that the integrated circuit must have to be placed at the first location.

16. The system of claim 10 , wherein the identifying code comprises at least one of a one-dimensional, two-dimensional, and three-dimensional bar code, wherein the different performance parameters are retrieved from a registration system maintained by a first e

Assignees

• Xilinx Inc

Inventors

• Klein Matthew H
• Teo Wei Yee Jocelyn
• Taylor Craig E

Classifications

• G06F30/00

  Computer-aided design [CAD] · CPC title

• G06Q30/0627 Primary

  by specifying product or service characteristics, e.g. product dimensions · CPC title

• G06F16/903

  Querying (for retrieval from the web G06F16/953) · CPC title

• G06F21/30

  Authentication, i.e. establishing the identity or authorisation of security principals · CPC title

• G06K7/10

  by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation · CPC title