Machine learning-based classification in parasitic extraction automation for circuit design and verification

Patent metadata

Field	Value
Publication number	US-11275883-B2
Application number	US-202016788545-A
Country	US
Kind code	B2
Filing date	Feb 12, 2020
Priority date	Feb 12, 2020
Publication date	Mar 15, 2022
Grant date	Mar 15, 2022

Abstract

This application discloses a computing system implementing a parasitic extraction tool to generate a parasitic model from physical design layout of an integrated circuit. The computing system also can implement a machine-learning classifier that, when trained with a training data set, can classify the physical design layout based on physical or electrical characteristics associated with the physical design layout, and can utilize the classification to select a set of scaling coefficients. The computing system can apply the selected set of the scaling coefficients to adjust coupling capacitances in the parasitic model and generate a parasitic netlist for the physical design layout. The computing system can generate the training data set by determining sets of the scaling coefficients from the test physical design layouts and labeling the test physical design layouts with the sets of the scaling coefficients.

First claim

The invention claimed is:

1. A method comprising:
classifying, by a computing system implementing a parasitic extraction tool, a physical design layout of an integrated circuit by generating a feature vector that describes physical characteristics associated with the physical design layout and utilizing the feature vector to classify the physical design layout according to a structural density of the physical design layout;
selecting, by the computing system implementing the parasitic extraction tool, a set of scaling coefficients based on the classification of the physical design layout, which associate the structural density of the physical design layout to the selected set of the scaling coefficients;
generating, by the computing system implementing the parasitic extraction tool, a parasitic model for the physical design layout, wherein the parasitic model includes an electrical representation of nets extracted from the physical design layout; and
adjusting, by the computing system implementing the parasitic extraction tool, coupling capacitances in the parasitic model using the selected set of the scaling coefficients.

2. The method of claim 1 , wherein the classifying of the physical design layout is performed by a machine-learning classifier trained with a training data set including test physical design layouts labeled with sets of scaling coefficients.

3. The method of claim 2 , further comprising generating, by the computing system, the training data set by determining the sets of the scaling coefficients from the test physical design layouts and labeling the test physical design layouts with the sets of the scaling coefficients.

4. The method of claim 3 , wherein determining the sets of the scaling coefficients from the test physical design layouts further comprises:
generating parasitic models for the test physical design layouts using different setting configurations for a parasitic extraction tool;
selecting, for each of the test physical design layouts, a setting configuration of the parasitic extraction tool based, at least in part, on the parasitic models;
clustering the parasitic models into groups based on the selected settings of the parasitic extraction tool; and
determining a set of the scaling coefficients for each of the groups of the parasitic models based on geometric information in the test physical design layouts.

5. The method of claim 4 , wherein the selecting, for each of the test physical design layouts, of the setting configuration of the parasitic extraction tool further comprises:
comparing, for each of the test physical design layouts, the parasitic models generated using different setting configurations against reference models associated with the test physical design layouts; and
selecting, for each of the test physical design layouts, the setting configuration of the parasitic extraction tool having smallest differences to the reference models determined with the comparison.

6. The method of claim 4 , wherein the determination of the set of the scaling coefficients for each of the groups of the parasitic models is performed by iteratively adjusting, for each of the groups of the parasitic models, the scaling coefficients in the set based on differences between reference models associated with the group and the parasitic models having the adjusted the scaling coefficients.

7. The method of claim 3 , wherein labeling the test physical design layouts with the sets of the scaling coefficients further comprises:
applying the sets of the scaling coefficients to parasitic models generated from the test physical design layouts, which adjusts coupling capacitances in the parasitic models; and
assigning each of the test physical design layouts one of the sets of the scaling coefficients based, at least in part, on a comparison of the parasitic models having adjusted coupling capacitances against reference models associated with the test physical design layouts.

8. A system comprising:
a memory device configured to store machine-readable instructions; and
a computing system including one or more processing devices, in response to executing the machine-readable instructions, configured to:
classify a physical design layout of an integrated circuit by generating a feature vector that describes physical characteristics associated with the physical design layout and utilizing the feature vector to classify the physical design layout according to a structural density of the physical design layout;
select a set of scaling coefficients based on the classification of the physical design layout, which associate the structural density of the physical design layout to the selected set of the scaling coefficients;
generate a parasitic model for the physical design layout, wherein the parasitic model includes an electrical representation of nets extracted from the physical design layout; and
adjust coupling capacitances in the parasitic model using the selected set of the scaling coefficients.

9. The system of claim 8 , wherein the one or more processing devices, in response to executing the machine-readable instructions, are configured to classify the physical design layout using a machine-learning classifier trained with a training data set including test physical design layouts labeled with sets of scaling coefficients.

10. The system of claim 9 , wherein the one or more processing devices, in response to executing the machine-readable instructions, are configured to generate the training data set by determining the sets of the scaling coefficients from the test physical design layouts and labeling the test physical design layouts with the sets of the scaling coefficients.

11. The system of claim 10 , wherein the determining of the sets of the scaling coefficients from the test physical design layouts further comprises:
generating parasitic models for the test physical design layouts using different setting configurations for a parasitic extraction tool;
selecting, for each of the test physical design layouts, a setting configuration of the parasitic extraction tool based, at least in part, on the parasitic models;
clustering the parasitic models into groups based on the selected settings of the parasitic extraction tool; and
determining a set of the scaling coefficients for each of the groups of the parasitic models based on geometric information in the test physical design layouts.

12. The system of claim 11 , wherein the selecting, for each of the test physical design layouts, of the setting configuration of the parasitic extraction tool further comprises:
comparing, for each of the test physical design layouts, the parasitic models generated using different setting configurations against reference models associated with the test physical design layouts; and
selecting, for each of the test physical design layouts, the setting configuration of the parasitic extraction tool having smallest differences to the reference models determined with the comparison.

13. The system of claim 11 , wherein the determination of the set of the scaling coefficients for each of the groups of the parasitic models is performed by iteratively adjusting, for each of the groups of the parasitic models, the scaling coefficients in the set based on differences between reference models associated with the group and the parasitic models having the adjusted the scaling coefficients.

14. An apparatus including a memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
classifying a physical design layout of an integrated circuit by generating a feature vector th

Assignees

• Siemens Ind Software Inc

Inventors

• Kourkoulos Vasileios
• Du Lin
• Chen Renbo

Classifications

• G06N20/00

  Machine learning · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/27 Primary

  using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model · CPC title