Integrated circuit, electronic device including the same, and operating method thereof

Patent metadata

Field	Value
Publication number	US-11271584-B2
Application number	US-202117159197-A
Country	US
Kind code	B2
Filing date	Jan 27, 2021
Priority date	Jul 8, 2020
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

Disclosed is an integrated circuit, which includes a DTC block including DTCs, receiving a first reference signal and a first division signal, and outputting a second reference signal and a second division signal based on the first reference signal, the first division signal, and control codes, a TDC comparing phases of the second reference signal and the second division signal and outputting a comparison signal, a digital loop filter filtering the comparison signal, an oscillator generating an output signal based on the filtered comparison signal, a delta-sigma modulator outputting a first signal and a quantized noise signal based on first and second division ratio signals, a divider dividing a frequency of the output signal based on the first signal and outputting the first division signal, and a probability modulator generating the control codes based on the quantized noise signal. Probability density functions of the control codes are time-invariant.

First claim

What is claimed is:

1. An integrated circuit comprising:
a digital-to-time converter (DTC) block including a plurality of DTCs, which receives a first reference signal and a first division signal and outputs a second reference signal and a second division signal based on the first reference signal, the first division signal, and a plurality of control codes;
a time-to-digital converter (TDC) which compares a phase of the second reference signal and a phase of the second division signal and outputs a comparison signal;
a digital loop filter which filters the comparison signal;
an oscillator which generates an output signal based on the filtered comparison signal;
a delta-sigma modulator which outputs a first signal and a quantized noise signal based on a first division ratio signal and a second division ratio signal;
a divider which divides a frequency of the output signal based on the first signal and outputs the first division signal; and
a probability modulator which generates the plurality of control codes based on the quantized noise signal,
wherein probability density functions of the plurality of control codes are time-invariant.

2. The integrated circuit of claim 1 , wherein a linear combination of the plurality of control codes corresponds to the quantized noise signal.

3. The integrated circuit of claim 1 , wherein the oscillator includes a ring oscillator.

4. The integrated circuit of claim 1 , wherein the DTC block includes a first DTC and a second DTC,
wherein the first DTC delays the first reference signal in a time domain during a first delay time in response to a first control code of the plurality of control codes, and
wherein the second DTC delays the first division signal in the time domain during a second delay time in response to a second control code of the plurality of control codes.

5. The integrated circuit of claim 1 , wherein the DTC block includes a first DTC and a second DTC connected in series,
wherein the first DTC delays the first division signal in a time domain during a first delay time in response to a first control code of the plurality of control codes and outputs a first intermediate signal, and
wherein the second DTC delays the first intermediate signal in the time domain during a second delay time in response to a second control code of the plurality of control codes.

6. The integrated circuit of claim 1 , wherein the probability modulator includes a uniform random number generator, and
wherein the probability modulator generates the plurality of control codes based on a uniform random number generated from the uniform random number generator.

7. The integrated circuit of claim 1 , wherein the plurality of control codes include a first control code and a second control code,
wherein a probability density function corresponding to the first control code from among the plurality of probability density functions and a probability density function corresponding to the second control code from among the plurality of probability density functions follow a uniform distribution follow a uniform distribution, and
wherein a difference between the first control code and the second control code corresponds to the quantized noise signal.

8. The integrated circuit of claim 1 , further comprising:
a DTC gain controller which modulates the plurality of control codes and provides the plurality of modulated control codes to the DTC block,
wherein the DTC block operates based on the plurality of modulated control codes.

9. An electronic device comprising:
a processor; and
a communication device which receives data from the outside under control of the processor, wherein the communication device includes:
a delta-sigma modulator which outputs a first signal and a quantized noise signal based on a first division ratio signal and a second division ratio signal;
a probability modulator which generates a plurality of control codes based on the quantized noise signal;
a digital-to-time converter (DTC) block including a plurality of DTCs, the DTC block which receives a first reference signal and a first division signal and outputs a second reference signal and a second division signal based on the first reference signal, the first division signal, and the plurality of control codes;
a time-to-digital converter (TDC) which compares a phase of the second reference signal and a phase of the second division signal and outputs a comparison signal;
a digital loop filter which filters the comparison signal;
an oscillator which generates an output signal based on the filtered comparison signal; and
a circuit block which receives the first signal and the output signal and generates the first division signal from the output signal in response to the first signal,

wherein probability density functions of the plurality of control codes are time-invariant.

10. The electronic device of claim 9 ,
wherein a linear combination of the plurality of control codes corresponds to the quantized noise signal.

11. The electronic device of claim 9 , wherein the plurality of control codes include a first control code and a second control code,
wherein a probability density function corresponding to the first control code from among the plurality of probability density functions and a probability density function corresponding to the second control code from among the plurality of probability density functions follow a uniform distribution follow a uniform distribution, and
wherein a difference between the first control code and the second control code corresponds to the quantized noise signal.

12. The electronic device of claim 9 , wherein the circuit block includes one of a multi-modulus divider (MMD) and a phase selector.

13. The electronic device of claim 9 , further comprising:
a DTC gain controller which modulates the plurality of control codes and provides the plurality of modulated control codes to the DTC block,
wherein the DTC block operates based on the plurality of modulated control codes.

14. The electronic device of claim 9 , wherein the probability modulator includes a uniform random number generator, and
wherein the probability modulator generates the plurality of control codes based on a uniform random number generated from the uniform random number generator.

15. A method comprising:
generating a plurality of control codes based on a first signal associated with a quantized noise of a delta-sigma modulator;
delaying a reference signal and a division signal in a time domain based on the plurality of control codes, respectively; and
generating an output signal based on the delayed reference signal and the delayed division signal,
wherein probability density functions of the plurality of control codes are time-invariant.

16. The method of claim 15 ,
wherein a linear combination of the plurality of control codes corresponds to the quantized noise.

17. The method of claim 15 , wherein the plurality of control codes include a first control code and a second control code, and
wherein the generating of the plurality of control codes includes:
generating a first intermediate code and a second intermediate code based on the first signal and a uniform distribution function;
determining one of the first intermediate code and the second intermediate code as the second control code based on a sign of the first signal; and
generating the first control code being a difference between the second control code and the first signal.

18. The method of claim 17 , wherein the delaying of the reference signal

Assignees

• Korea Advanced Inst Sci & Tech
• Korean Advanced Institute Of Science And Tech

Inventors

• Choi Jaehyouk
• Seong Taeho
• Lee Yongsun
• Hwang Chanwoong
• Park Hangi

Classifications

• H03M7/3004

  Digital delta-sigma modulation · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H03M3/322 Primary

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, e.g. by using stored correction values, H03M3/378) · CPC title