Intelligent power module control method for resonant converter

Patent metadata

Field	Value
Publication number	US-11271559-B2
Application number	US-201916595063-A
Country	US
Kind code	B2
Filing date	Oct 7, 2019
Priority date	Mar 20, 2017
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

A method of generating a gate drive signal for driving a control terminal of a power switch includes detecting a system input signal; determining a signal pulse of the system input signal being a first signal pulse following a power up event, or following an idle period, or following removal of a fault condition; and in response, generating a soft gate drive signal to drive the control terminal of the power switch to softly turn on the power switch. In another embodiment, the method includes determining a duration of the on period of the system input signal exceeding a maximum on duration and in response, disabling the gate drive signal to turn off the power switch; and determining a deassertion transition of the system input signal and in response, blocking the system input signal from the gate drive signal for a minimum off duration.

First claim

What is claimed is:

1. A method of generating a gate drive signal for driving a control terminal of a power switch where the control terminal controls the current flow between first and second power terminals of the power switch, the method comprising:
detecting a power up event in response to a power supply voltage increasing above a threshold voltage;
detecting a system input signal, the system input signal determining an on-period and off-period of the power switch;
determining a signal pulse of the system input signal being a first signal pulse following the power up event and in response to the determining, generating a soft gate drive signal to drive the control terminal of the power switch with a slowly rising voltage to softly turn on the power switch;
generating a normal gate drive signal to drive the control terminal of the power switch in response to signal pulses of the system input signal subsequent to the first signal pulse;
determining a signal pulse of the system input signal being a first signal pulse following an idle period of the system input signal and in response to the determining, generating the soft gate drive signal to drive the control terminal of the power switch with a slowly rising voltage to softly turn on the power switch; and
determining a signal pulse of the system input signal being a first signal pulse following removal of a fault condition and in response to the determining, generating the soft gate drive signal to drive the control terminal of the power switch with a slowly rising voltage to softly turn on the power switch.

2. The method of claim 1 , wherein the fault condition comprises one of an under-voltage of a positive power supply voltage, an over-voltage of the positive power supply voltage, an on-period exceeding a maximum on duration, and an over-temperature condition.

3. The method of claim 1 , wherein determining the signal pulse of the system input signal being a first signal pulse following an idle period of the system input signal comprises:
determining a signal pulse of the system input signal being a first signal pulse following an idle period having a time duration exceeding a maximum idle duration.

4. The method of claim 3 , further comprising:
determining the signal pulse of the system input signal being a first signal pulse following an idle period having a time duration less than the maximum idle duration; and
generating a normal gate drive signal to drive the control terminal of the power switch in response to signal pulses of the system input signal subsequent to the idle period.

5. The method of claim 1 , further comprising:
generating the normal gate drive signal to drive the control terminal of the power switch in response to signal pulses of the system input signal subsequent to the first signal pulse after the idle period.

6. The method of claim 1 , further comprising:
generating the normal gate drive signal to drive the control terminal of the power switch in response to signal pulses of the system input signal subsequent to the first signal pulse after the removal of the fault condition.

7. The method of claim 1 , further comprising:
monitoring a deassertion transition of the system input signal; and
blocking the system input signal from driving the control terminal of the power switch for a minimum off duration.

8. The method of claim 1 , further comprising:
monitoring a duration of the on period of the system input signal; and
turning off the power switch in response to the duration of the on period exceeding a maximum on duration.

9. The method of claim 1 , further comprising:
detecting an over-voltage condition across the power switch during an off-period of the power switch; and
driving the power switch with a clamped voltage to turn on the power switch to dissipate the over-voltage.

10. The method of claim 1 , further comprising:
detecting an operating condition of the power switch;
generating a fault indicator signal in response to a fault condition being detected;
blocking the system input signal from driving the power switch in response to the fault indicator signal being asserted; and
in response to the fault indicator signal being deasserted, returning to detecting the system input signal.

11. The method of claim 1 , wherein the fault condition comprises one of an under-voltage of the positive power supply voltage, an over-voltage of the positive power supply voltage, and an over-temperature condition.

12. A method of generating a gate drive signal for driving a control terminal of a power switch where the control terminal controls the current flow between first and second power terminals of the power switch, the method comprising:
detecting a system input signal, the system input signal determining an on-period and off-period of the power switch;
generating the gate drive signal in response to the system input signal;
determining a duration of the on period of the system input signal exceeding a maximum on duration and in response to the determining, disabling the gate drive signal to turn off the power switch; and
determining a deassertion transition of the system input signal and in response to the determining, blocking the system input signal from the gate drive signal for a minimum off duration.

13. The method of claim 12 , further comprising:
asserting a fault indicator signal in response to the system input signal exceeding the maximum on duration;
in response to the fault indicator signal being asserted, disabling the gate drive signal to turn off the power switch and blocking the system input signal from the gate drive signal; and
in response to the fault indicator signal being deasserted, returning to detecting the system input signal.

14. The method of claim 12 , further comprising:
in response to the expiration of the minimum off duration, returning to detect the system input signal.

15. The method of claim 12 , further comprising:
detecting a signal pulse of the system input signal being a first signal pulse following a power up event, the power up event being indicative of a power supply voltage increasing above a threshold voltage;
in response to detecting the first signal pulse following the power up event, generating a soft gate drive signal to drive the control terminal of the power switch with a slowly rising voltage to softly turn on the power switch; and
generating a normal gate drive signal to drive the control terminal of the power switch in response to signal pulses of the system input signal subsequent to the first signal pulse.

16. The method of claim 15 , further comprising:
detecting a signal pulse of the system input signal being a first signal pulse following an idle period of the system input signal; and
in response to detecting the first signal pulse, generating the soft gate drive signal to drive the control terminal of the power switch with a slowly rising voltage to softly turn on the power switch.

17. The method of claim 15 , further comprising:
detecting a signal pulse of the system input signal being a first signal pulse following removal of a fault condition; and
in response to detecting the first signal pulse, generating the soft gate drive signal to drive the control terminal of the power switch with a slowly rising voltage to softly turn on the power switch.

18. The method of claim 17 , wherein the fault condition comprises one of an under-voltage of a positive power supply voltage, an over-voltage of the positive power supply voltage, an on-period exceeding a maximum on duration,

Assignees

• Alpha & Omega Semiconductor Cayman Ltd

Inventors

• Suh Bum-Seok
• Cho Wonjin
• Tran Son

Classifications

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title

• H10W72/527

  Multiple bond wires having different sizes · CPC title

• H10W72/07552

  changes in structures or sizes · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title