Over-voltage protection circuit for a drive transistor

Patent metadata

Field	Value
Publication number	US-2016105017-A1
Application number	US-201414509427-A
Country	US
Kind code	A1
Filing date	Oct 8, 2014
Priority date	Oct 8, 2014
Publication date	Apr 14, 2016
Grant date	—

Abstract

A drive transistor is connected to a resonant load in a low-side drive configuration. The voltage across the conduction terminals of the drive transistor is sensed and compared to an over-voltage threshold. An over-voltage signal is asserted in response to the comparison. The drive transistor is controlled by a PWM control signal in normal mode. In response to the assertion of the over-voltage signal, the drive transistor is forced to turn on (irrespective of the PWM control signal) to relieve the over-voltage condition. Operation of the circuit may be disabled or forced into soft start mode in response to the assertion of the over-voltage signal. Additionally, the pulse width of the PWM control signal may be reduced in response to the assertion of the over-voltage signal.

First claim

What is claimed is:

1 . A circuit, comprising:
a drive transistor having a control terminal configured to receive a drive signal and having a first conduction terminal and a second conduction terminal, wherein said first conduction terminal is configured for connection to a load circuit; a sense circuit configured to sense a voltage across the first and second conduction terminals; a comparator circuit configured to compare the sensed voltage to voltage threshold and generate a signal indicative of an over-voltage condition; and drive circuitry configured to generate said drive signal in response to a pulse width modulation (PWM) signal, said drive circuit including a force on circuit actuated in response to said signal indicative of the over-voltage condition to force said drive transistor to turn on irrespective of the PWM signal.

2 . The circuit of claim 1 , wherein the drive transistor is an insulated gate bi-polar transistor (IGBT).

3 . The circuit of claim 1 , further comprising said load circuit.

4 . The circuit of claim 3 , wherein said load circuit is a resonant tank circuit.

5 . The circuit of claim 1 , wherein the drive transistor is a low-side drive transistor.

6 . The circuit of claim 1 , further comprising a PWM generator circuit configured to generate said PWM signal.

7 . The circuit of claim 6 , wherein the PWM generator circuit includes a soft start circuit, and wherein the soft start circuit is actuated in response to said signal indicative of the over-voltage condition.

8 . The circuit of claim 6 , wherein the PWM generator circuit includes an excessive over-voltage condition detection circuit configured to disable generation of the PWM signal if a number of signals indicative of the over-voltage condition are received in excess of a shut down threshold.

9 . The circuit of claim 6 , wherein the PWM generator circuit includes an excessive over-voltage condition detection circuit configured to reduce a pulse width of the PWM signal if a number of signals indicative of the over-voltage condition are received in excess of a reduction threshold.

10 . The circuit of claim 9 , wherein the excessive over-voltage condition detection circuit is further configured to incrementally reduce pulse width of the PWM signal with each reception of the signal indicative of the over-voltage condition in excess of said reduction threshold.

11 . The circuit of claim 10 , wherein the excessive over-voltage condition detection circuit is still further configured to disable generation of the PWM signal if the number of signals indicative of the over-voltage condition received is in excess of a shut down threshold.

12 . The circuit of claim 6 , wherein the PWM generator circuit includes a disable circuit configured to disable generation of the PWM signal in response to said signal indicative of the over-voltage condition.

13 . A method, comprising:
applying a drive signal to a control terminal of a drive transistor including a conduction terminal configured for connection to a load circuit; sensing a voltage across the first and second conduction terminals; comparing the sensed voltage to voltage threshold; generating a signal indicative of an over-voltage condition in response to said comparing; and generating said drive signal in response to a pulse width modulation (PWM) signal, wherein generating further comprises forcing said drive transistor to turn on in response to said signal indicative of the over-voltage condition irrespective of the PWM signal.

14 . The method of claim 13 , further comprising actuating a soft start process for PWM signal generation in response to said signal indicative of the over-voltage condition.

15 . The method of claim 13 , further comprising disabling PWM signal generation in response to said signal indicative of the over-voltage condition.

16 . The method of claim 13 , further comprising disabling PWM signal generation if a number of signals indicative of the over-voltage condition are received in excess of a shut down threshold.

17 . The method of claim 13 , further comprising reducing a pulse width of the PWM signal if a number of signals indicative of the over-voltage condition are received in excess of a reduction threshold.

18 . The method of claim 17 , further comprising incrementally reducing pulse width of the PWM signal with each reception of the signal indicative of the over-voltage condition in excess of said reduction threshold.

19 . The method of claim 18 , further comprising disabling generation of the PWM signal if the number of signals indicative of the over-voltage condition received is in excess of a shut down threshold.

20 . A circuit, comprising:
a drive transistor having a control terminal configured to receive a drive signal and having a first conduction terminal and a second conduction terminal, wherein said first conduction terminal is configured for connection to a load circuit; a sense circuit configured to sense a voltage across the first and second conduction terminals; a comparator circuit configured to compare the sensed voltage to voltage threshold and generate a signal indicative of an over-voltage condition; a pulse width modulation (PWM) signal generator configured to generate a PWM signal; and a drive circuit configured to generate said drive signal in response to said PWM signal if the signal indicative of an over-voltage condition is not asserted and otherwise force said drive transistor to turn on if the signal indicative of the over-voltage condition is asserted.

21 . The circuit of claim 20 , wherein the PWM signal generator comprises a soft start circuit actuated when the signal indicative of the over-voltage condition is asserted.

22 . The circuit of claim 20 , wherein the PWM signal generator comprises a disable circuit actuated when the signal indicative of the over-voltage condition is asserted.

23 . The circuit of claim 20 , wherein the PWM signal generator comprises a pulse width control circuit configured to reduce a pulse width of the PWM signal in response to assertion of the signal indicative of the over-voltage condition.

24 . The circuit of claim 23 , wherein the pulse width control circuit is further configured to incrementally reduce the pulse width of the PWM signal with each assertion of the signal indicative of the over-voltage condition.

Assignees

• St Microelectronics Int Nv
• St Microelectronics Srl
• St Microelectronics Srl

Inventors

• Mallik Ranajay
• Abbatelli Luigi
• Catalisano Giuseppe
• Jain Akshat

Classifications

• H02H1/0007

  concerning the detecting means (in general G01R or other subclasses of G01; reed switches H01H71/2445) · CPC title

• H02H7/205 Primary

  for controlled semi-conductors which are not included in a specific circuit arrangement · CPC title

• H03K17/0828 Primary

  in composite switches · CPC title

• H03K17/168

  in composite switches · CPC title

• H05B6/062

  for cooking plates or the like · CPC title