Integrated circuit

Patent metadata

Field	Value
Publication number	US-11271150-B2
Application number	US-202016866114-A
Country	US
Kind code	B2
Filing date	May 4, 2020
Priority date	Sep 28, 2018
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

An integrated circuit is provided. The integrated circuit includes a metallization pattern, a dielectric layer, and plural memory devices. The metallization pattern has plural first conductive features and a second conductive feature. The dielectric layer is over the metallization pattern, in which the dielectric layer has a first portion over the first conductive features and a second portion over the second conductive feature. The memory devices are at least partially in the first portion of the dielectric layer and respectively connected with the first conductive features. The first portion of the dielectric layer has a plurality of side parts respectively surrounding the memory devices and an extending part connecting the side parts to each other, and a thickness of the second portion is greater than a thickness of the extending part of the first portion of the dielectric layer.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a metallization pattern having a plurality of first conductive features and a second conductive feature;
a dielectric layer over the metallization pattern, wherein the dielectric layer has a first portion over the first conductive features and a second portion over the second conductive feature; and
a plurality of memory devices at least partially in the first portion of the dielectric layer and respectively connected with the first conductive features, wherein the first portion of the dielectric layer has a plurality of side parts respectively surrounding the memory devices and an extending part connecting the side parts to each other, and a thickness of the second portion is greater than a thickness of the extending part of the first portion of the dielectric layer.

2. The integrated circuit of claim 1 , wherein the thickness of the second portion of the dielectric layer is equal to or less than a thickness of the side parts of the first portion of the dielectric layer.

3. The integrated circuit of claim 1 , further comprising:
a dummy memory device at least partially in the second portion of the dielectric layer.

4. The integrated circuit of claim 1 , further comprising:
a conductive via in the second portion of the dielectric layer and connected with the second conductive feature.

5. A device, comprising:
a first metallization pattern having a first conductive feature and a second conductive feature;
a first dielectric layer over the first metallization pattern;
a first memory device having a first bottom electrode via in the first dielectric layer and over the first conductive feature, wherein the first dielectric layer has a first portion extending along sidewalls of the firs bottom electrode via and a second portion extending laterally from the first portion; and
a second memory device having a second bottom electrode via in the first dielectric layer and over the second conductive feature, wherein the first dielectric layer has a third portion extending along sidewalls of the second bottom electrode via and a fourth portion extending laterally from the third portion, and a thickness of the fourth portion of the first dielectric layer is greater than a thickness of the second portion of the first dielectric layer.

6. The device of claim 5 , wherein a top surface of the fourth portion of the first dielectric layer is higher than a top surface of the second portion of the first dielectric layer.

7. The device of claim 5 , wherein the second portion of the first dielectric layer extends laterally from the first portion of the first dielectric layer to the fourth portion of the first dielectric layer.

8. The device of claim 5 , further comprising:
a third memory device having a third bottom electrode via in the first dielectric layer, wherein the first dielectric layer has a fifth portion extending along sidewalls of the third bottom electrode via, and the fourth portion of the first dielectric layer extends laterally from the third portion of the first dielectric layer to the fifth portion of the first dielectric layer.

9. The device of claim 5 , wherein the thickness of the second portion of the first dielectric layer is less than a thickness of the first portion of the first dielectric layer.

10. The device of claim 5 , wherein the thickness of the fourth portion of the first dielectric layer is less than a thickness of the third portion of the first dielectric layer.

11. The device of claim 5 , further comprising:
a second dielectric layer over the first and second memory devices, wherein the second memory device has a top electrode over the second bottom electrode via, and a top surface of the top electrode of the second memory device is in contact with the second dielectric layer.

12. The device of claim 11 , further comprising:
a second metallization pattern in the second dielectric layer, wherein the first memory device has a top electrode over the first bottom electrode via, and a top surface of the top electrode of the first memory device is in contact with the second metallization pattern.

13. An integrated circuit, comprising:
a substrate having a cell region and a logic region;
a first metallization pattern having a first conductive feature and a second conductive feature respectively over the cell region and the logic region;
an etch stop layer over the first metallization pattern, wherein the etch stop layer has a first portion and a second portion respectively over the cell region and the logic region;
a metal-containing compound layer over the first portion of the etch stop layer;
a dielectric layer over the metal-containing compound layer;
a memory device having a bottom electrode via, a bottom electrode over the bottom electrode via, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element, wherein the bottom electrode via extends through the dielectric layer, the metal-containing compound layer, and the etch stop layer to the first conductive feature; and
a third conductive feature extending through the etch stop layer to the second conductive feature.

14. The integrated circuit of claim 13 , wherein the second portion of the etch stop layer is free from coverage of the metal-containing compound layer and the dielectric layer.

15. The integrated circuit of claim 13 , wherein the dielectric layer comprises:
a first portion extending along a top surface of the metal-containing compound layer, wherein the bottom electrode via extends through the first portion of the dielectric layer; and
a second portion extending along the top surface of the metal-containing compound layer, wherein the second portion of the dielectric layer is between the first portion of the dielectric layer and the logic region, and a thickness of the second portion of the dielectric layer is greater than a thickness of the first portion of the dielectric layer.

16. The integrated circuit of claim 15 , wherein the dielectric layer further comprises:
a third portion extending along sidewalls of the bottom electrode via and connected with the first portion of the dielectric layer.

17. The integrated circuit of claim 15 , further comprising:
a dummy memory device having a dummy bottom electrode via, wherein the dummy bottom electrode via extends through the second portion of the dielectric layer, the metal-containing compound layer, and the etch stop layer.

18. The integrated circuit of claim 17 , wherein the dummy memory device further comprises a dummy bottom electrode over the dummy bottom electrode via, a dummy resistance switching element over the dummy bottom electrode, and a dummy top electrode over the dummy resistance switching element.

19. The integrated circuit of claim 17 , further comprising:
a second metallization pattern having a fourth conductive feature and a fifth conductive feature respectively over the cell region and the logic region, wherein the fourth conductive feature is connected with the top electrode of the memory device, the fifth conductive feature is connected with the third conductive feature, and the dummy memory device is disconnected from the second metallization pattern.

20. The integrated circuit of claim 13 , wherein the metal-containing compound layer is an aluminum-containing compound layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Tai-Yen
• Huang Chien-Chung
• Chen Yu-Shu
• Yang Sin-Yi
• Wang Chen-Jung
• Lin Han-Ting
• Ting Chih-Yuan
• Shieh Jyu-Horng
• Wei Hui-Hsien

Classifications

• H01L27/222

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic

• H01L43/12 Primary

  Electricity · mapped topic

• H01L27/224

  Electricity · mapped topic