Semiconductor device and power converter

Patent metadata

Field	Value
Publication number	US-11271084-B2
Application number	US-201816605216-A
Country	US
Kind code	B2
Filing date	May 30, 2018
Priority date	Jun 6, 2017
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

The present invention relates to a semiconductor device having trench gates. The semiconductor device includes the following: a first semiconductor layer; a first semiconductor region selectively disposed in the upper layer of the first semiconductor layer; a second semiconductor region in contact with the first semiconductor region; a third semiconductor region on the bottom surfaces of the first and second semiconductor regions; gate trenches provided to penetrate the first and third semiconductor regions in the thickness direction of the first and third semiconductor regions to reach the inside of the first semiconductor layer; a field-reducing region on the bottom of each gate trench; and connection layers arranged in the first semiconductor layer at intervals so as to be each in contact with at least one of sidewalls of the gate trenches, the connection layers each electrically connecting the field-reducing region to the third semiconductor region.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first semiconductor layer of a first conductivity type;
a first semiconductor region of the first conductivity type selectively disposed in an upper layer of the first semiconductor layer;
a second semiconductor region of a second conductivity type disposed in the upper layer of the first semiconductor layer so as to be in contact with the first semiconductor region;
a third semiconductor region of the second conductivity type disposed on bottom surfaces of the first and second semiconductor regions;
a plurality of gate trenches provided to penetrate the first and third semiconductor regions in a thickness direction of the first and third semiconductor regions, the plurality of gate trenches each comprising a bottom surface reaching an inside of the first semiconductor layer, the plurality of gate trenches being in a form of stripes and extending only in one direction in a plan view;
a field-reducing region of the second conductivity type disposed on the bottom surface of each of the plurality of gate trenches;
an interlayer insulating film comprising contact openings above the first and second semiconductor regions;
a plurality of connection layers arranged in the first semiconductor layer at intervals so as to be each in contact with at least one of sidewalls of a corresponding one of the plurality of gate trenches in a second direction perpendicular to a first direction parallel with a direction in which the plurality of gate trenches extend, the intervals between the plurality of connection layers adjacent to each other in the first direction being set to be as large as or larger than an interval at which the plurality of gate trenches are arranged, the plurality of connection layers each electrically connecting the field-reducing region to the third semiconductor region;
a first main electrode disposed over the interlayer insulating film and filled in the contact openings; and
a second main electrode disposed on a main surface of the first semiconductor layer, the main surface being opposite from where the first main electrode is disposed,
wherein the first semiconductor layer has an off-angle greater than 0 degrees,
the first direction is parallel with an off-direction, and
the plurality of connection layers are spaced from each other in the first direction.

2. The semiconductor device according to claim 1 , wherein
the first semiconductor layer comprises a silicon-carbide layer,
the first semiconductor layer has an off-angle greater than 0 degrees in a <11-20> direction, and
the plurality of gate trenches each comprise a sidewall surface comprising a (1-100) plane or (−1100) plane.

3. The semiconductor device according to claim 1 , wherein
each of the plurality of connection layers is provided to extend in the second direction from the sidewall of the corresponding one of the plurality of gate trenches, and
the plurality of connection layers are shorter in the second direction than a length between the plurality of gate trenches adjacent to each other.

4. The semiconductor device according to claim 1 , wherein
the plurality of connection layer each comprise
a first connection layer provided to be in contact with the corresponding one of the plurality of gate trenches, and
a second connection layer located to be farther from the corresponding one of the plurality of gate trenches than the first connection layer, and

the first connection layer has an impurity concentration higher than an impurity concentration of the second connection layer.

5. The semiconductor device according to claim 1 , wherein the plurality of connection layers each have an impurity concentration of 1×10 17 cm −3 or more and 5×10 19 cm −3 or less.

6. The semiconductor device according to claim 1 , wherein the plurality of connection layers each have a length of 0.3 μm or more in a thickness direction of the first semiconductor layer.

7. The semiconductor device according to claim 1 , wherein
the plurality of connection layers each comprise
a first connection layer provided to be in contact with the corresponding one of the plurality of gate trenches, and
a second connection layer located to be farther from the corresponding one of the plurality of gate trenches than the first connection layer, and

the first and second connection layers are of the second conductivity type.

8. The semiconductor device according to claim 1 , wherein
the plurality of connection layers each comprise
a first connection layer provided to be in contact with the corresponding one of the plurality of gate trenches, and
a second connection layer located to be farther from the corresponding one of the plurality of gate trenches than the first connection layer,

the first connection layer is of the first conductivity type, and
the second connection layer is of the second conductivity type.

9. The semiconductor device according to claim 1 , wherein each of the plurality of connection layers is provided to have such a length in a thickness direction of the first semiconductor layer as to decrease along with distance in the second direction from the sidewall of the corresponding one of the plurality of gate trenches.

10. The semiconductor device according to claim 1 , wherein the plurality of connection layers are disposed on only one of the sidewalls of the corresponding one of the plurality of gate trenches in the second direction.

11. The semiconductor device according to claim 1 , wherein the plurality of connection layers are provided alternately on one of the sidewalls and the other sidewall of the corresponding one of the plurality of gate trenches in the second direction.

12. The semiconductor device according to claim 1 , wherein the plurality of connection layers are provided to be in contact with the third semiconductor region and the second semiconductor region.

13. The semiconductor device according to claim 1 , further comprising
a current spreading region of the first conductivity type disposed in the first semiconductor layer, the current spreading region being in contact with each of the plurality of connection layers and the field-reducing region,
wherein the current spreading region is provided to have an impurity concentration higher than that of the first semiconductor layer.

14. The semiconductor device according to claim 1 , further comprising a second semiconductor layer of the first conductivity type disposed on a bottom surface of the third semiconductor region.

15. The semiconductor device according to claim 1 , wherein
the plurality of gate trenches comprise
a first gate trench comprising an inner-wall surface covered with a gate insulating film, the first gate trench being filled with a gate electrode, and
a second gate trench comprising an inner-wall surface covered with a Schottky electrode, the second gate trench being filled with the first main electrode, and

the first gate trench comprises an upper portion covered with the interlayer insulating film.

16. The semiconductor device according to claim 1 , wherein
the plurality of connection layers are of the second conductivity type,
each of the plurality of connection layers and the field-reducing region form a pillar of the second conductivity type,
the first semiconductor layer between the pillars of the second conductivity type adjacent to each other forms a pillar of the first conductivity type, and
the pillar of the first conductivity type and the pillar of the second conductivity type form a super-junction structure.

Assignees

• Mitsubishi Electric Corp

Inventors

• Fukui Yutaka
• Sugawara Katsutoshi
• Hatta Hideyuki
• Koketsu Hidenori
• Tanaka Rina
• Miyata Yusuke

Classifications

• H10D64/232

  Emitter electrodes for IGBTs · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D30/668

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D8/60

  Schottky-barrier diodes · CPC title