Memory device

Patent metadata

Field	Value
Publication number	US-11270980-B2
Application number	US-202016916979-A
Country	US
Kind code	B2
Filing date	Jun 30, 2020
Priority date	Mar 7, 2017
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

First claim

What is claimed is:

1. A memory device comprising:
a first memory cell array including a plurality of first electrode layers, a first conductive layer, and a first semiconductor pillar,
the first electrode layers being stacked in a first direction,
the first conductive layer being provided above the first electrode layers in the first direction,
the first semiconductor pillar extending through the first electrode layers in the first direction, the first semiconductor pillar being connected to the first conductive layer;
a first contact plug extending in the first direction through the first electrode layers, the first contact plug being connected to the first conductive layer;
a second memory cell array provided above the first memory cell array in the first direction, the second memory cell array including a plurality of second electrode layers, a second conductive layer, and a second semiconductor pillar,
the second electrode layers being stacked in the first direction,
the second conductive layer being provided above the second electrode layers in the first direction,
the second semiconductor pillar extending in the first direction through the second electrode layers, the second semiconductor pillar being connected to the second conductive layer;
a second contact plug extending in the first direction through the second electrode layers, the second contact plug being connected to the second conductive layer; and
a connection metal provided between the first and second memory cell arrays, the connection metal electrically connecting the first contact plug and the second conductive layer.

2. The device according to claim 1 , wherein
the first memory cell array includes first memory cells provided respectively between each of the first electrode layers and the first semiconductor pillar, and
the second memory cell array includes second memory cells provided respectively between each of the second electrode layers and the second semiconductor pillar.

3. The device according to claim 1 , wherein
the first memory cell array further includes a first interconnection electrically connected to the first semiconductor pillar, the first semiconductor pillar having a first end and a second end opposite to the first end, the first end being connected to the first conductive layer, the second end being electrically connected to the first interconnection, and
the second memory cell array further includes a second interconnection electrically connected to the second semiconductor pillar, the second semiconductor pillar having a third end and a fourth end opposite to the third end, the third end being connected to the second conductive layer, the fourth end being electrically connected to the second interconnection.

4. The device according to claim 1 , wherein
the first contact plug is electrically insulated from the first electrode layers by a first insulating film, and
the second contact plug is electrically insulated from the second electrode layers by a second insulating film.

5. The device according to claim 1 , wherein
the first memory cell array includes a first memory film provided between the first semiconductor pillar and the first electrode layers, and
the second memory cell array includes a second memory film provided between the second semiconductor pillar and the first electrode layers.

6. The device according to claim 1 , wherein
the first and second conductive layers each include a metal layer and a semiconductor layer stacked in the first direction, and
the first and second semiconductor pillars each are connected to the semiconductor layer.

7. The device according to claim 1 , wherein
the connection metal electrically connects the first contact plug and the second contact plug.

8. The device according to claim 1 , wherein
the connection metal is provided between the first contact plug and the second contact plug.

9. The device according to claim 1 , wherein
the first memory cell array further includes a plurality of other first electrode layers stacked in the first direction, the first electrode layers and the other first electrode layers being arranged in a second direction crossing the first direction, and
the first contact plug is provided between the first electrode layers and the other first electrode layers.

10. The device according to claim 9 , wherein
the second memory cell array further includes a plurality of other second electrode layers stacked in the first direction, the second electrode layers and the other second electrode layers being arranged in the second direction, and
the second contact plug is provided between the second electrode layers and the other second electrode layers.

11. The device according to claim 1 , further comprising:
a circuit driving the first memory cell array and the second memory cell array, wherein the first memory cell array is provided between the second memory cell array and the circuit.

12. The device according to claim 11 , further comprising:
a connecting conductor provided in a periphery around the first memory cell array and the second memory cell array, the connecting conductor electrically connecting the circuit and the first and second memory cell arrays.

13. The device according to claim 12 , wherein
the connecting conductor electrically connects one of the first electrode layers and one of the second electrode layers to the circuit.

14. The device according to claim 13 , wherein
the connecting conductor includes first and second conductive parts, the first conductive part being electrically connected to one of the first electrode layers in a periphery around the first memory cell array, the second conductive part being electrically connected to the one of the second electrode layers in a periphery around the second memory cell array.

Assignees

• Kioxia Corp

Inventors

• Tagami Masayoshi
• Katsumata Ryota
• Iijima Jun
• Shimizu Tetsuya
• Usui Takamasa
• Fujita Genki

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title