3-D non-volatile memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9515074-B2
Application number	US-201514795766-A
Country	US
Kind code	B2
Filing date	Jul 9, 2015
Priority date	Dec 14, 2010
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A three-dimensional (3-D) non-volatile memory device includes a plurality of word line structures extended in parallel and including a plurality of interlayer dielectric layers and a plurality of word lines that are alternately stacked over a substrate, a plurality of channels protruding from the substrate configured to penetrate the plurality of interlayer dielectric layers and the plurality of word lines, and an air gap formed between the plurality of word line structures.

First claim

What is claimed is:

1. A method of manufacturing a three-dimensional (3-D) non-volatile memory device, the method comprising:
forming a plurality of memory cells stacked along channels protruded from a substrate, wherein the channels penetrate a plurality of first material layers and a plurality of second material layers that are alternately stacked over the substrate;
forming a plurality of word line structures extended in parallel;
forming a slit between the plurality of word line structures by etching the plurality of first material layers and the plurality of second material layers between neighboring channels; and
forming an air gap between the plurality of word line structures by forming an insulating layer to cover a top of the slit,
wherein forming a plurality of memory cells comprises:
forming the plurality of first material layers and the plurality of second material layers alternately over the substrate;
forming trenches for the channels by etching the plurality of first material layers and the plurality of second material layers; and
forming the channels in the trenches.

2. The method of claim 1 , further comprising siliciding edge regions of the plurality of word lines, exposed by sidewalls of the word line structures, after forming the slit.

3. The method of claim 1 , further comprising recessing the plurality of first material layers, exposed by sidewalls of the word line structures, after forming the slit.

4. The method of claim 3 , wherein recessing the plurality of first material layers is performed using a remote plasma process or a wet etch process.

5. The method of claim 1 , further comprising forming a charge blocking layer, a charge trap layer, and a tunnel insulating layer over inner walls of the trenches, after forming the trenches.

6. The method of claim 1 , further comprising:
forming a plurality of recess regions by removing the plurality of second material layers exposed by the slit, after forming the slit and
forming interlayer dielectric layers or word lines in the plurality of recess regions.

7. The method of claim 6 , wherein the second material layer is a sacrificial layer.

8. The method of claim 6 , further comprising forming a tunnel insulating layer, a charge trap layer, and a charge blocking layer, after forming the trenches for the channels or forming the plurality of recess regions.

9. A method of manufacturing a three-dimensional (3-D) non-volatile memory device, the method comprising:
forming a plurality of memory cells stacked along channels protruded from a substrate, wherein the channels penetrate a plurality of first material layers and a plurality of second material layers that are alternately stacked over the substrate;
forming a plurality of word line structures extended in parallel;
forming a slit between the plurality of word line structures by etching the plurality of first material layers and the plurality of second material layers between neighboring channels; and
forming an air gap between the plurality of word line structures by forming an insulating layer to cover a top of the slit,
wherein forming a plurality of memory cells comprises:
forming the plurality of first material layers and the plurality of second material layers alternately over the substrate;
forming trenches for the channels by etching the plurality of first material layers and the plurality of second material layers;
forming a plurality of floating regions by recessing the plurality of first material layers, exposed by inner walls of the trenches;
forming a charge blocking layer on an entire surface of the floating regions;
faulting a plurality of floating gates by burying a conductive layer in the plurality of floating regions on the charge blocking layer;
forming a tunnel insulating layer on the inner walls of the trenches; and
forming the channels in the trenches in which the tunnel insulating layer is formed.

10. The method of claim 9 , further comprising:
forming a plurality of recess regions by removing the plurality of second material layers exposed by the slit, after forming the slit and
forming interlayer dielectric layers or word lines in the plurality of recess regions.

11. The method of claim 10 , wherein the second material layer is a sacrificial layer.

12. A method of manufacturing a three-dimensional (3-D) non-volatile memory device, the method comprising:
forming a plurality of memory cells stacked along channels protruded from a substrate, wherein the channels penetrate a plurality of first material layers and a plurality of second material layers that are alternately stacked over the substrate;
forming a plurality of word line structures extended in parallel;
forming a slit between the plurality of word line structures by etching the plurality of first material layers and the plurality of second material layers between neighboring channels; and
forming an air gap between the plurality of word line structures by forming an insulating layer to cover a top of the slit,
wherein forming a plurality of memory cells comprises:
forming trenches for U-shaped channels, including a first trench, formed by etching a pipe gate, and at least two second trenches coupled to the first trench and configured to penetrate the plurality of first material layers and the plurality of second material layers;
forming a charge blocking layer, a charge trap layer, and a tunnel insulating layer over inner walls of the trenches; and
forming the U-shaped channels in the trenches.

13. The method of claim 12 , wherein forming a slit comprises etching the plurality of first material layers and the plurality of second material layers between neighboring U-shaped channels, etching the plurality of first material layers and the plurality of second material layers between the second channels included in each of the U-shaped channels, or etching the plurality of first material layers and the plurality of second material layers between neighboring U-shaped channels and between the second channels included in each of the U-shaped channels.

Assignees

• Sk Hynix Inc

Inventors

• Whang Sung Jin
• Lee Ki Hong

Classifications

• H10W10/021 Primary

  of air gaps · CPC title

• H10W10/20 Primary

  Air gaps · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D30/689

  Vertical floating-gate IGFETs · CPC title

• H10D30/6728

  Vertical TFTs · CPC title