Enabling magnetic films in inductors integrated into semiconductor packages

Patent metadata

Field	Value
Publication number	US-11270959-B2
Application number	US-201815933599-A
Country	US
Kind code	B2
Filing date	Mar 23, 2018
Priority date	Mar 23, 2018
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

Techniques for fabricating a semiconductor package comprising inductor features and a magnetic film are described. For one technique, fabricating a package includes: forming inductor features comprising a pad and a conductive line on a first build-up layer; forming a raised pad structure on the first build-up layer by fabricating a pillar structure on the pad, wherein a size of the pillar structure is approximately equal or equal to a corresponding size of the pad such that the pillar structure and the pad are aligned or minimally misaligned relative to each other; encapsulating the inductor features and the raised pad structure in a magnetic film; planarizing the magnetic film until top surfaces of the raised pad structure and magnetic film are co-planar; depositing an additional layer on the top surfaces; and forming a via on the raised pad structure by removing portions of the additional layer above the raised pad structure.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a plurality of inductor features on a first build-up layer, the plurality of inductor features comprising a pad and a conductive line;
a raised pad structure on the first build-up layer, the raised pad structure comprising a pillar structure on the pad, wherein a size of the pillar structure is approximately equal or equal to a corresponding size of the pad such that the pillar structure and the pad are aligned or minimally misaligned relative to each other;
a magnetic film encapsulating the plurality of inductor features and the raised pad structure, the magnetic film comprising one or more magnetic fillers, wherein top surfaces of the raised pad structure and the magnetic film are co-planar;
an additional layer on the top surfaces of the raised pad structure and the magnetic film, the additional layer in direct contact with the magnetic film; and
a via on the top surface of the raised pad structure, the via being through the additional layer.

2. The semiconductor package of claim 1 , wherein the raised pad structure has a z-height that is larger than a z-height of each of the plurality of inductor features that is not the raised pad structure.

3. The semiconductor package of claim 1 , wherein a mechanical planarization technique is used to planarize the top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar.

4. The semiconductor package of claim 1 , wherein a size of the via is less than or equal to a corresponding size of the raised pad structure.

5. The semiconductor package of claim 1 , further comprising a conductive structure over the via.

6. The semiconductor package of claim 5 , further comprising a second plurality of inductor features on the additional layer.

7. The semiconductor package of claim 6 , further comprising a magnetic paste encapsulating one or more inductor features selected from the second plurality of inductor features.

8. The semiconductor package of claim 1 , wherein the additional layer comprises one or more of: (i) a second build-up layer; and (ii) a photoimageable dielectric (PID) layer.

9. The semiconductor package of claim 1 , wherein the magnetic film is a film comprised of: (i) one or more of an epoxy resin, a polyimide, and a glass-reinforced epoxy laminate material; and (ii) the one or more magnetic fillers.

10. The semiconductor package of claim 9 , wherein the magnetic film comprises an organic dielectric epoxy laminate film having the one or more magnetic fillers therein.

11. The semiconductor package of claim 10 , wherein at least one of the one or more magnetic fillers formed from one or more of: (i) a ferromagnetic material; and
(ii) a ferrimagnetic material.

12. The semiconductor package of claim 11 , wherein at least one of the one or more magnetic fillers is formed from one or more of: iron (Fe), cobalt (Co), nickel (Ni), any ferrite that includes Fe and oxygen (O), ferrous oxide (FeO), and a metal alloy comprising one or more of Fe, Co, and Ni.

13. A method of forming a cored or coreless semiconductor package, comprising:
forming a plurality of inductor features on a first build-up layer, the plurality of inductor features comprising a pad and a conductive line;
forming a raised pad structure on the first build-up layer by fabricating a pillar structure on the pad, wherein a size of the pillar structure is approximately equal or equal to a corresponding size of the pad such that the pillar structure and the pad are aligned or minimally misaligned relative to each other;
encapsulating the plurality of inductor features and the raised pad structure in a magnetic film, the magnetic film comprising one or more magnetic fillers;
planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar;
depositing an additional layer on the top surfaces of the raised pad structure and the magnetic film, the additional layer in direct contact with the magnetic film; and
forming a via on the top surface of the raised pad structure by removing one or more portions of the additional layer above the raised pad structure.

14. The method of claim 13 , wherein the raised pad structure has a z-height that is larger than a z-height of each of the plurality of inductor features that is not the raised pad structure.

15. The method of claim 13 , wherein planarizing a top surface of the magnetic film comprises using a mechanical planarization technique to planarize the top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar.

16. The method of claim 13 , wherein a size of the via is less than or equal to a corresponding size of the raised pad structure to mitigate or eliminate any misalignment between the pillar structure and the pad.

17. The method of claim 13 , further comprising forming a conductive structure over the via.

18. The method of claim 17 , further comprising forming a second plurality of inductor features on the additional layer.

19. The method of claim 18 , further comprising encapsulating one or more inductor features from the second plurality of inductor features in a magnetic paste.

20. A semiconductor package, comprising:
a plurality of inductor features on a first build-up layer, the plurality of inductor features comprising a pad and a conductive line;
a raised pad structure on the first build-up layer, the raised pad structure comprising a pillar structure on the pad, wherein a size of the pillar structure is less than a corresponding size of the pad;
a magnetic film encapsulating the plurality of inductor features and the raised pad structure, the magnetic film comprising one or more magnetic fillers, wherein top surfaces of the raised pad structure and the magnetic film are co-planar;
an additional layer on the top surfaces of the raised pad structure and the magnetic film, the additional layer in direct contact with the magnetic film; and
a via on the top surface of the raised pad structure, the via being through the additional layer.

21. The semiconductor package of claim 20 , wherein the raised pad structure has a z-height that is larger than a z-height of each of the plurality of inductor features that is not the raised pad structure.

22. The semiconductor package of claim 20 , wherein the magnetic film is a film comprised of: (i) one or more of an epoxy resin, a polyimide, and a glass-reinforced epoxy laminate material; and (ii) the one or more magnetic fillers.

23. The semiconductor package of claim 20 , wherein at least one of the one or more magnetic fillers formed from one or more of: (i) a ferromagnetic material; and
(ii) a ferrimagnetic material.

24. The semiconductor package of claim 20 , wherein the additional layer comprises one or more of: (i) a second build-up layer; and (ii) a photoimageable dielectric (PID) layer.

25. The semiconductor package of claim 20 , further comprising:
a second plurality of inductor features on the additional layer; and
a magnetic paste encapsulating one or more inductor features selected from the second plurality of inductor features.

26. A semiconductor package, comprising:
a plurality of inductor features on a first build-up layer, the plurality of inductor features comprising a pad and a conductive line;
a raised pad structure on the first build-

Assignees

• Intel Corp

Inventors

• Darmawikarta Kirstof
• Pietambaram Srinivas
• Chatterjee Prithwish
• Boyapati Sri Ranga Sai
• Jen Wei Lun

Classifications

• H10W90/728

  between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/098

  Applying pastes or inks, e.g. screen printing (H10W70/095 takes precedence) · CPC title

• H10W70/66

  Conductive materials thereof · CPC title