Integrated circuit package and method of forming same

Patent metadata

Field	Value
Publication number	US-11270920-B2
Application number	US-201916536716-A
Country	US
Kind code	B2
Filing date	Aug 9, 2019
Priority date	Aug 14, 2018
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a glass core layer, where the glass core layer includes a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer. The package also includes a die disposed in the cavity of the glass core layer, an encapsulant disposed in the cavity between the die and a sidewall of the cavity, a first patterned conductive layer disposed adjacent the first major surface of the glass core layer, and a second patterned conductive layer disposed adjacent the second major surface of the glass core layer. The die is electrically connected to at least one of the first and second patterned conductive layers.

First claim

What is claimed is:

1. An integrated circuit package, comprising:
a substrate comprising a glass core layer, the glass core layer comprising a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer;
a die disposed in the cavity of the glass core layer;
an encapsulant disposed in the cavity between the die and a sidewall of the cavity;
a first patterned conductive layer disposed adjacent the first major surface of the glass core layer;
a dielectric layer disposed between the first patterned conductive layer and the first major surface of the glass core layer;
a second patterned conductive layer disposed adjacent the second major surface of the glass core layer;
a conductive via disposed in the glass core layer and extending between the first and second major surfaces of the glass core layer, wherein the conductive via is electrically connected to at least one of the first and second patterned conductive layers; and
a device disposed on the first patterned conductive layer, wherein the device is electrically connected to the die;
wherein the die is electrically connected to at least one of the first and second patterned conductive layers.

2. The package of claim 1 , wherein the die is electrically connected to each of the first and second patterned conductive layers.

3. The package of claim 1 , wherein the dielectric layer is laminated to the glass core layer.

4. The package of claim 1 , wherein the encapsulant comprises a portion of the dielectric layer.

5. The package of claim 1 , further comprising a field plate disposed within the dielectric layer, wherein the field plate is spaced apart from the die.

6. The package of claim 5 , wherein the die further comprises a field termination structure disposed on an outer surface of the die that faces the field plate, wherein at least a portion of the field plate overlaps the field termination structure in a direction orthogonal to the first major surface of the glass core layer.

7. The package of claim 1 , further comprising a second dielectric layer disposed between the second patterned conductive layer and the second major surface of the glass core layer.

8. The package of claim 1 , wherein the die comprises a high-voltage electrical component.

9. The package of claim 8 , wherein the high-voltage electrical component is operable with a potential of at least 500 volts.

10. The package of claim 1 , wherein the die comprises at least one of a field effect transistor, a metal oxide semiconductor field effect transistor, an insulated gate bipolar junction transistor, a thyristor, a bipolar transistor, a diode, a MOS-controlled thyristor, a resistor, and a capacitor.

11. An implantable medical device comprising the integrated circuit package of claim 1 .

12. An integrated circuit package, comprising:
a substrate comprising a glass core layer, the glass core layer comprising a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer;
a high-voltage electrical component disposed in the cavity of the glass core layer;
an encapsulant disposed in the cavity between the high-voltage electrical component and a sidewall of the cavity;
a first patterned conductive layer disposed adjacent the first major surface of the glass core layer;
a second patterned conductive layer disposed adjacent the second major surface of the glass core layer; and
a conductive via disposed in the glass core layer and extending between the first and second major surfaces of the glass core layer, wherein the conductive via is electrically connected to at least one of the first and second patterned conductive layers;
wherein the high-voltage electrical component is electrically connected to at least one of the first and second patterned conductive layers.

13. The package of claim 12 , wherein the high-voltage electrical component is operable with a potential of at least 500 volts.

14. The package of claim 12 , wherein the high-voltage electrical component is electrically connected to each of the first and second patterned conductive layers.

15. The package of claim 12 , further comprising a dielectric layer disposed between the first patterned conductive layer and the first major surface of the glass core layer.

16. The package of claim 15 , further comprising a field plate disposed within the dielectric layer, wherein the field plate is spaced apart from the high-voltage electrical component.

17. The package of claim 16 , wherein the high-voltage electrical component further comprises a field termination structure disposed on an outer surface of the high-voltage electrical component that faces the field plate, wherein at least a portion of the field plate overlaps the field termination structure in a direction orthogonal to the first major surface of the glass core layer.

18. An implantable medical device comprising an integrated circuit package, wherein the integrated circuit package comprises:
a substrate comprising a glass core layer, the glass core layer comprising a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer;
a die disposed in the cavity of the glass core layer;
an encapsulant disposed in the cavity between the die and a sidewall of the cavity;
a first patterned conductive layer disposed adjacent the first major surface of the glass core layer;
a second patterned conductive layer disposed adjacent the second major surface of the glass core layer; and
a conductive via disposed in the glass core layer and extending between the first and second major surfaces of the glass core layer, wherein the conductive via is electrically connected to at least one of the first and second patterned conductive layers;
wherein the die is electrically connected to at least one of the first and second patterned conductive layers.

19. The device of claim 18 , further comprising a housing and a power source, wherein the integrated circuit package and the power source are disposed within the housing.

20. The device of claim 18 , wherein the die is electrically connected to each of the first and second patterned conductive layers.

Assignees

• Medtronic Inc

Inventors

• Kim Chunho
• Henschel Mark E

Classifications

• H10W74/01

  Manufacture or treatment · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/692 Primary

  Ceramics or glasses · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title