Memory device with increased electrode resistance to reduce transient selection current

Patent metadata

Field	Value
Publication number	US-11264567-B2
Application number	US-201916688309-A
Country	US
Kind code	B2
Filing date	Nov 19, 2019
Priority date	Nov 19, 2019
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

Various embodiments of a three-dimensional cross-point (3D X-point) memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features. In any case, the resulting increased memory cell resistance causes a reduction in the transient selection current for the given memory cell.

First claim

What is claimed is:

1. A memory device, comprising:
an array of memory cells, each memory cell arranged between a word line and a bit line of the memory device, each memory cell to include:
a stack of layers to include a phase change layer, a selector layer, a first electrode that is beneath the selector layer, and one or both of:
a second electrode between the phase change layer and the selector layer; and
a third electrode above the phase change layer; and

an interface layer in direct contact with the first electrode, the interface layer comprising one or more of tungsten, silicon, aluminum, oxygen, boron, or nitrogen, wherein a combined resistance of the first electrode and the interface layer is about 20% higher than a resistance of the second electrode and/or the third electrode.

2. The memory device of claim 1 , wherein the interface layer has a thickness between about 20 Å and about 50 Å.

3. The memory device of claim 1 , wherein the first electrode comprises carbon and nitrogen.

4. The memory device of claim 1 , wherein the interface layer comprises tungsten, silicon, and nitrogen.

5. An electronic device comprising a chip package that includes the memory device of claim 1 .

Assignees

• Intel Corp

Inventors

• Venkatesan Srivatsan
• Mantegazza Davide
• Gorman John
• Elango Iniyan Soundappa
• Fugazza Davide
• Redaelli Andrea
• Pellizzer Fabio

Classifications

• G11C13/003

  Cell access · CPC title

• G11C2213/76

  Array using an access device for each cell which being not a transistor and not a diode · CPC title

• H01L45/1608

  Electricity · mapped topic

• H01L45/144

  Electricity · mapped topic

• H01L45/1253 Primary

  Electricity · mapped topic