Semiconductor device including dummy gate patterns and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11264482-B2
Application number	US-201916572681-A
Country	US
Kind code	B2
Filing date	Sep 17, 2019
Priority date	Apr 23, 2019
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

A semiconductor device may include: a dummy gate structure including a first gate pattern in which dummy gate lines extending in one direction are connected to each other on a substrate, and a second gate pattern in which dummy gate lines extending in the one direction are connected to each other on the same line with the first gate pattern; and a third gate pattern extending in parallel with the dummy gate structure on one side of the dummy gate structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
a dummy gate structure including a first gate pattern in which first dummy gate lines extending in a first direction are connected to each other on a substrate, and a second gate pattern in which second dummy gate lines extending in the first direction are connected to each other, the second dummy gate lines being aligned with the first dummy gate lines; and
a third gate pattern extending in the first direction in parallel with the dummy gate structure on a first side of the dummy gate structure.

2. The semiconductor device of claim 1 ,
wherein the first gate pattern comprises:
a first dummy gate line extending in the first direction;
a second dummy gate line disposed in parallel with the first dummy gate line; and
a first bridge pattern connecting one end of the first dummy gate line to one end of the second dummy gate line; and

wherein the second gate pattern comprises:
a third dummy gate line extending on the same line as the first dummy gate line;
a fourth dummy gate line extending on the same line as the second dummy gate line, and disposed adjacent to the third dummy gate line; and
a second bridge pattern connecting one end of the third dummy gate line to one end of the fourth dummy gate line.

3. The semiconductor device of claim 2 , further comprising:
a fourth gate pattern extending in the first direction in parallel with the dummy gate structure at a second side of the dummy gate structure,
wherein at least one of the third gate pattern and the fourth gate pattern is a real gate line.

4. The semiconductor device of claim 2 ,
wherein the first bridge pattern has a U-shape, and
wherein the second bridge pattern has an inverted U-shape and is symmetrical to the first bridge pattern.

5. The semiconductor device of claim 4 ,
wherein in the first bridge pattern, a portion nearer the second bridge pattern has a greater width than a portion farther from the second bridge pattern, and
wherein in the second bridge pattern, a portion nearer the first bridge pattern has a greater width than a portion farther from the first bridge pattern.

6. The semiconductor device of claim 2 , further comprising:
a third bridge pattern disposed between the first bridge pattern and the second bridge pattern and connecting the first bridge pattern to the second bridge pattern,
wherein a width of the third bridge pattern is smaller than a width of the first bridge pattern.

7. The semiconductor device of claim 6 , wherein the first, second, and third bridge patterns are connected to each other to have an X-shape.

8. A semiconductor device comprising:
a cell region including active fins extending in a first direction and real gate lines extending in a second direction, which intersects the first direction, and crossing the active fins; and
a dummy region on which dummy gate structures extending in parallel with the real gate lines are disposed,
wherein the dummy gate structures include:
a pair of upper dummy gate lines extending in the second direction and disposed in parallel with each other;
an upper bridge pattern connecting the pair of upper dummy gate lines to each other;
a pair of lower dummy gate lines disposed to be spaced apart from the pair of upper dummy gate lines and the upper bridge pattern in the second direction; and
a lower bridge pattern connecting the pair of lower dummy gate lines to each other.

9. The semiconductor device of claim 8 , wherein a portion of the dummy gate structures overlap the cell region and the dummy region.

10. The semiconductor device of claim 8 ,
wherein the pair of upper dummy gate lines comprises:
a first dummy gate line disposed on the cell region; and
a second dummy gate line disposed on the dummy region, and

wherein the upper bridge pattern is disposed over the cell region and the dummy region.

11. The semiconductor device of claim 10 , wherein the first dummy gate line crosses the active fins, and the second dummy gate line is disposed adjacent to ends of the active fins.

12. The semiconductor device of claim 10 , wherein the upper bridge pattern overlaps the active fins.

13. The semiconductor device of claim 8 ,
wherein the cell region comprises:
a first cell region on which first active fins are disposed;
a second cell region on which second active fins are disposed; and
a middle region disposed between the first cell region and the second cell region, and

wherein the pair of upper dummy gate lines are disposed on the first cell region, and the pair of lower dummy gate lines are disposed on the second cell region.

14. The semiconductor device of claim 13 , wherein the upper bridge pattern and the lower bridge pattern are disposed on the middle region.

15. The semiconductor device of claim 14 , wherein the upper bridge pattern is disposed on the first cell region, the pair of lower dummy gate lines extend to the first cell region, and the lower bridge pattern is disposed on the first cell region.

16. The semiconductor device of claim 8 , wherein the upper bridge pattern and the lower bridge pattern are connected to each other.

17. The semiconductor device of claim 8 , wherein the dummy region does not comprise the active fins, and the semiconductor device further comprises a dummy gate structure disposed on the cell region.

18. A semiconductor device comprising:
a first gate pattern extending in a first direction on a substrate; and
a second gate pattern disposed adjacent to the first gate pattern in the first direction,
wherein the first gate pattern comprises a first protrusion in which an inner sidewall of the first gate pattern, which is adjacent to the second gate pattern, protrudes toward the second gate pattern, and
wherein the second gate pattern comprises a second protrusion in which an inner sidewall of the second gate pattern, which is adjacent to the first gate pattern, protrudes toward the first protrusion.

19. The semiconductor device of claim 18 ,
wherein the first gate pattern further comprises a first recess in which an outer sidewall is recessed concavely toward the first protrusion, and
wherein the second gate pattern further comprises a second recess in which an outer sidewall is concavely recessed toward the second protrusion.

20. The semiconductor device of claim 19 , wherein the first protrusion and the second protrusion are in contact with each other.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Donghyun
• Song Inhyun
• Jeon Yeongmin
• Park Sejin
• Park Juyun
• Baek Jonghoon
• Shin Taeyeon
• Jeong Sooyeon

Classifications

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D84/014

  the gate conductors having different materials or different implants · CPC title

• H10D30/611 Primary

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title