Isolator integrated circuits with package structure cavity and fabrication methods

Patent metadata

Field	Value
Publication number	US-11264369-B2
Application number	US-202016859345-A
Country	US
Kind code	B2
Filing date	Apr 27, 2020
Priority date	Dec 30, 2016
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

In described examples, an integrated circuit includes a leadframe structure, which includes electrical conductors. A first coil structure is electrically connected to a first pair of the electrical conductors of the leadframe structure. The first coil structure is partially formed on a semiconductor die structure. A second coil structure is electrically connected to a second pair of the electrical conductors of the leadframe structure. The second coil structure is partially formed on the semiconductor die structure. A molded package structure encloses portions of the leadframe structure. The molded package structure exposes portions of the first and second pairs of the electrical conductors to allow external connection to the first and second coil structures. The molded package structure includes a cavity to magnetically couple portions of the first and second coil structures.

First claim

What is claimed is:

1. A method of fabricating an integrated circuit (IC), the method comprising:
mounting at least one semiconductor die on a leadframe structure;
connecting bond wires between bond pads of the semiconductor die and corresponding electrical conductors of the leadframe structure;
forming a sacrificial material over a portion of the semiconductor die;
forming a molded package material over the semiconductor die, the bond wires and portions of the leadframe structure and the sacrificial material to create a molded package structure;
sublimating the sacrificial material to create an internal cavity defined by an interior surface of the molded package structure, the internal cavity including at least a portion of an isolation barrier between first and second circuit structures, at least one of the first or second circuit structures associated with the semiconductor die, the first circuit structure electrically connected to a first pair of the electrical conductors of the leadframe structure, the first circuit structure including a light source configured to generate a light signal, the second circuit structure spaced from the first circuit structure and electrically connected to a second pair of the electrical conductors of the leadframe structure, the second circuit structure including a light sensor at least partially facing the light source to receive the light signal, the molded package structure exposing portions of the first and second pairs of the electrical conductors to allow external connection to the first and second circuit structures, the cavity providing a solid-free optical path for the light signal between the first and second circuit structures, the optical path extending in a direction corresponding to a straight line extending directly from the first circuit structure to the second circuit structure;
connecting a first pair of die pads of the semiconductor die to the first pair of the electrical conductors of the leadframe structure;
connecting a second pair of die pads of the semiconductor die to the second pair of the electrical conductors of the leadframe structure;
forming a first sacrificial material layer over a portion of the semiconductor die;
forming a first coil structure partially on the first sacrificial material layer, the first coil structure electrically connected to the first pair of the electrical conductors of the leadframe structure;
forming a second sacrificial material layer over a portion of the first coil structure;
forming a second coil structure partially on the second sacrificial material layer, the second coil structure electrically connected to the second pair of the electrical conductors of the leadframe structure;
forming a third sacrificial material layer over a portion of the second coil structure; and
forming the molded package material over the semiconductor die, the bond wires and portions of the leadframe structure, the first and second coil structures, and the sacrificial material layers to create the molded package structure;
wherein sublimating the sacrificial material includes sublimating the sacrificial material layers to create the internal cavity to provide an electrical isolation barrier between portions of the first and second coil structures.

2. The method of claim 1 , further comprising: forming a ferrous material layer over a portion of one of the semiconductor die and one of the coil structures before forming the molded package material.

3. The method of claim 1 , further comprising:
mounting first and second semiconductor dies on the leadframe structure;
forming the first coil structure partially on the first semiconductor die; and
forming the second coil structure partially on the second semiconductor die.

Assignees

• Texas Instruments Inc

Inventors

• Male Barry Jon
• Cook Benjamin Stassen
• Neidorff Robert Alan
• Kummerl Steve

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W80/743

  having disposition changed during the connecting · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/075

  of bond wires · CPC title