ASIC package with photonics and vertical power delivery

Patent metadata

Field	Value
Publication number	US-11264358-B2
Application number	US-201916567766-A
Country	US
Kind code	B2
Filing date	Sep 11, 2019
Priority date	Sep 11, 2019
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets.

First claim

The invention claimed is:

1. An integrated circuit (IC) package comprising:
a substrate;
an IC die mounted to a first surface of the substrate;
one or more photonic modules attached to the first surface of the substrate;
one or more serializer/deserializer (SerDes) interfaces directly connecting the IC die to the one or more photonic modules; and
a voltage regulator mounted on a second surface of the substrate directly under the IC die, wherein the second surface of the substrate is opposite the first surface of the substrate.

2. The IC package of claim 1 , wherein the one or more SerDes interfaces include a plurality of copper traces; and
wherein the copper traces are deposited on the substrate.

3. The IC package of claim 1 , wherein each of the one or more photonic modules includes a controller, wherein each controller manages transmission of data between its respective photonic module and the IC die.

4. The IC package of claim 3 , wherein each of the one or more photonic modules further include a photonic integrated circuit (PIC) and fiber array.

5. The IC package of claim 4 , wherein each of the one or more SerDes interfaces includes a first side and a second, opposite side,
wherein for each of the SerDes interfaces, the first side connects to a respective photonic module and the second, opposite side connects to the IC die.

6. The IC package of claim 1 , wherein the IC package is configured to connect to a land grid array (LGA) socket.

7. The IC package of claim 6 , wherein power is delivered to the IC package via the LGA socket.

8. The IC package of claim 1 , wherein the one or more photonic modules are mounted to one or more additional substrates.

9. The IC package of claim 8 , wherein the one or more additional substrates are attached to the substrate via one or more sockets.

10. An application specific integrated circuit (ASIC) package
comprising:
a substrate;
an ASIC die mounted to a first surface of the substrate;
one or more photonic modules attached to the first surface of the substrate;
one or more serializer/deserializer (SerDes) interfaces directly connecting the ASIC die to the one or more photonic modules; and
a voltage regulator mounted on a second surface of the substrate directly under the IC die, wherein the second surface of the substrate is opposite the first surface of the substrate.

11. The ASIC package of claim 10 , wherein the one or more SerDes interfaces include a plurality of copper traces; and
wherein the copper traces are deposited on the substrate.

12. The ASIC package of claim 10 , herein each of the one or more photonic modules includes a controller, wherein each controller manages transmission of data between its respective photonic module and the ASIC die.

13. The ASIC package of claim 12 , wherein each of the one or more photonic modules further include a photonic integrated circuit (PIC) and fiber array.

14. The ASIC package of claim 13 , wherein each of the one or more SerDes interfaces includes a first side and a second, opposite side,
wherein for each of the SerDes interfaces, the first side connects to a respective photonic module and the second, opposite side connects to the ASIC die.

15. The ASIC package of claim 10 , wherein the substrate is configured to connect to a land grid array (LGA) socket.

16. The ASIC package of claim 15 , wherein power is delivered to the voltage regulator via the LGA socket.

17. The ASIC package of claim 10 , wherein the one or more photonic modules are mounted to one or more additional substrates.

18. The ASIC package of claim 17 , wherein the one or more additional substrates are attached to the substrate via one or more sockets.

Assignees

• Google Llc

Inventors

• Kwon Woon-Seong
• Kim Namhoon
• Kang Teckgyu
• Urata Ryohei

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title