Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2018090220-A1
Application number	US-201715448607-A
Country	US
Kind code	A1
Filing date	Mar 3, 2017
Priority date	Sep 26, 2016
Publication date	Mar 29, 2018
Grant date	—

Abstract

A semiconductor memory device includes memory cells, a word line connected to gates of the memory cells, and a control circuit configured to execute a write operation on the memory cells. The write operation includes a first program operation during which a first program voltage is applied to the word line, a first verify operation during which a first verification voltage is applied to the word line to determine whether or not the first program operation passed, a second program operation during which a second program voltage is applied to the word line, and a second verify operation during which a second verification voltage is applied to the word line to determine whether or not the second program operation passed. The control circuit is configured to execute at least one intervening program or verify operation between the first program operation and the first verify operation.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a plurality of memory cells; a word line electrically connected to gates of the memory cells; and a control circuit configured to execute a write operation on the memory cells, the write operation including a first program operation during which the control circuit applies a first program voltage to the word line, a first verify operation during which the control circuit applies a first verification voltage to the word line to determine whether or not the first program operation passed, a second program operation during which the control circuit applies a second program voltage, which is different from the first program voltage, to the word line, and a second verify operation during which the control circuit applies a second verification voltage, which is different from the first verification voltage, to the word line to determine whether or not the second program operation passed, wherein the control circuit is configured to execute at least one intervening program or verify operation between the first program operation and the first verify operation.

2 . The device according to claim 1 , wherein the first program voltage is higher than the second program voltage and the first verification voltage is higher than the second verification voltage.

3 . The device according to claim 1 , wherein the first program voltage is lower than the second program voltage and the first verification voltage is lower than the second verification voltage.

4 . The device according to claim 1 , wherein the at least one intervening program or verify operation includes the second program operation.

5 . The device according to claim 4 , wherein the write operation further includes a repeat operation of the first program operation which is carried out with the first program voltage stepped up to a higher level, the repeat operation being executed between the first verify operation and the second verify operation.

6 . The device according to claim 1 , wherein the control circuit is configured to execute at least one intervening program or verify operation between the second program operation and the second verify operation.

7 . The device according to claim 5 , wherein the at least one intervening program or verify operation includes the first verify operation.

8 . The device according to claim 7 , wherein the write operation further includes a repeat operation of the first program operation which is carried out with the first program voltage stepped up to a higher level, and the at least one intervening program or verify operation further includes the repeat operation that is executed after the first verify operation.

9 . The device according to claim 1 , wherein the write operation further includes a third program operation
a third program operation during which the control circuit applies a third program voltage, which is less than both the first program voltage and the second program voltage, to the word line, and a third verify operation during which the control circuit applies a second verification voltage, which is less than both the first verification voltage and the second verification voltage, to the word line to determine whether or not the third program operation passed, wherein the control circuit is configured to execute at least one intervening program or verify operation between the third program operation and the third verify operation.

10 . The device according to claim 9 , wherein the control circuit executes the third program operation after the first program operation has passed.

11 . The device according to claim 9 , wherein the control circuit executes the third program operation, and immediately thereafter, the second verify operation followed by a repeat operation of the second program operation.

12 . The device according to claim 9 , wherein the control circuit executes the third program operation, and immediately thereafter, a repeat operation of the second program operation.

13 . The device according to claim 1 , wherein the first program operation and the first verify operation are executed in a loop repeatedly up to a maximum number of loops until the first program operation passes the first verify operation, and each loop of the first program operation and the first verify operation has at least one intervening program or verify operation executed between the first program operation and the first verify operation.

14 . The device according to claim 1 , wherein the first and verify operations each include a read operation during which read data is sensed based on a timing of the strobe signal, and the control circuit adjusts the timing of the strobe signal based on a position of the word line.

15 . The device according to claim 1 , wherein the first and second verification voltages are two of three, seven, or fifteen different verification voltages.

16 . In a semiconductor memory device comprising a plurality of memory cells having gates thereof electrically connected to a word line and a control circuit, a method of executing a write operation on the memory cells, said method comprising:
executing a first program operation during which the control circuit applies a first program voltage to the word line; after executing the first program operation, executing a second program operation during which the control circuit applies a second program voltage, which is different from the first program voltage, to the word line; and after executing the second program operation, executing a first verify operation during which the control circuit applies a first verification voltage to the word line to determine whether or not the first program operation passed; and after executing the first verify operation, executing a second verify operation during which the control circuit applies a second verification voltage, which is different from the first verification voltage, to the word line to determine whether or not the second program operation passed.

17 . The method according to claim 16 , further comprising:
after executing the first verify operation and before executing the second verify operation, repeating the first program operation with the first program voltage stepped up to a higher level.

18 . The method according to claim 16 , wherein the first program voltage is higher than the second program voltage and the first verification voltage is higher than the second verification voltage.

19 . The method according to claim 16 , wherein the first program voltage is lower than the second program voltage and the first verification voltage is lower than the second verification voltage.

20 . The method according to claim 16 , further comprising:
executing a third program operation during which the control circuit applies a third program voltage, which is less than both the first program voltage and the second program voltage, to the word line; and executing a third verify operation during which the control circuit applies a second verification voltage, which is less than both the first verification voltage and the second verification voltage, to the word line to determine whether or not the third program operation passed, wherein at least one intervening program or verify operation is executed between the third program operation and the third verify operation.

Assignees

• Toshiba Memory Corp

Inventors

• Minagawa Hiroe
• Shirakawa Masanobu

Classifications

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/3486

  Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming · CPC title

• G11C11/5671 Primary

  using charge trapping in an insulator · CPC title

• G11C2211/563

  Multilevel memory reading aspects · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title