Computing accelerator using a lookup table

Patent metadata

Field	Value
Publication number	US-11262980-B2
Application number	US-202016919043-A
Country	US
Kind code	B2
Filing date	Jul 1, 2020
Priority date	Jan 9, 2018
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

A computing accelerator using a lookup table. The accelerator may accelerate floating point multiplications by retrieving the fraction portion of the product of two floating-point operands from a lookup table, or by retrieving the product of two floating-point operands of two floating-point operands from a lookup table, or it may retrieve dot products of floating point vectors from a lookup table. The accelerator may be implemented in a three-dimensional memory assembly. It may use approximation, the symmetry of a multiplication lookup table, and zero-skipping to improve performance.

First claim

What is claimed is:

1. A method for calculating a first function based on a first number and a second number, the method comprising:
forming an address from:
a first factor, the first factor being a factor of the first number and comprising a first portion of the first number and a second portion of the first number, and
a second factor, the second factor being a factor of the second number and comprising a first portion and a second portion of the second number, the address being formed by concatenating a portion of the first factor and a portion of the second factor; and

retrieving, from a location identified by the address, the first function based on the first factor and the second factor,
wherein the first number and the second number are in a same representation, the method further comprising calculating a second function based at least in part on the first function.

2. The method of claim 1 , wherein the first portion of the first number is a fraction portion of the first number.

3. The method of claim 1 , wherein the first number is a first floating-point number, and the second number is a second floating-point number, and wherein the calculating of the second function comprises calculating an exponent as
a sum of:
the second portion of the first number, and
the second portion of the second number;

less:
a left-shift number equal to a leading zero count in a 2n-bit product of:
a first number formed by appending a leading one to the first portion of the first factor, and
a second number formed by appending a leading one to the first portion of the second factor,

wherein:
n is one plus a bit-length of the first factor.

4. The method of claim 3 , further comprising determining the left-shift number with a digital logic circuit.

5. The method of claim 3 , further comprising retrieving, from a location identified by the address, the left-shift number.

6. The method of claim 1 , wherein the concatenating of the portion of the first factor and the portion of the second factor comprises concatenating the portion of the first factor and the portion of the second factor in order according to their respective values.

7. The method of claim 1 , wherein the portion of the first factor is an entire first factor, and the portion of the second factor is an entire second factor.

8. The method of claim 1 , wherein:
the portion of the first factor is:
less than the first factor in its entirety, and
a contiguous subset of bits of the first factor, including a most significant bit of the first factor; and

the portion of the second factor is:
less than the second factor in its entirety, and
a contiguous subset of bits of the second factor, including a most significant bit of the second factor.

9. The method of claim 1 , wherein the first factor is the first number in its entirety and the second factor is the second number in its entirety.

10. The method of claim 1 , further comprising creating a lookup table comprising the location identified by the address, the creating comprising:
calculating an element of the lookup table; and
storing the element in memory.

11. A system for calculating a first function based on a first number and a second number, the system comprising:
a processing circuit, and
a memory,
the processing circuit being configured to:
form an address from:
a first factor, the first factor being a factor of the first number and comprising a first portion of the first number and a second portion of the first number, and
a second factor, the second factor being a factor of the second number and comprising a first portion and a second portion of the second number, the address being formed by concatenating a portion of the first factor and a portion of the second factor; and

retrieve, from a location, in the memory, identified by the address, the first function based on the first factor and the second factor,

the processing circuit being further configured to calculate a second function based at least in part on the first function.

12. The system of claim 11 , wherein the memory is a three-dimensional memory assembly comprising:
a stack of two or more memory chips and
a logic chip comprising the processing circuit.

13. The system of claim 11 , wherein the first portion of the first number is a fraction portion of the first number.

14. The system of claim 11 , wherein the concatenating of the portion of the first factor and the portion of the second factor comprises concatenating the portion of the first factor and the portion of the second factor in order according to their respective values.

15. The system of claim 14 , wherein the portion of the first factor is the first factor in its entirety, and the portion of the second factor is the second factor in its entirety.

16. The system of claim 14 , wherein:
the portion of the first factor is:
less than an entire first factor, and
a contiguous subset of bits of the first factor, including a most significant bit of the first factor; and

the portion of the second factor is:
less than the second factor in its entirety, and
a contiguous subset of bits of the second factor, including a most significant bit of the second factor.

17. The system of claim 11 , wherein the first factor is the first number in its entirety and the second factor is the second number in its entirety.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Malladi Krishna T
• Gu Peng
• Zheng Hongzhong
• Brennan Robert

Classifications

• G06N3/045

  Combinations of networks · CPC title

• G06F7/4876 Primary

  Multiplying · CPC title

• G06F7/49936

  Normalisation mentioned as feature only · CPC title

• G06F7/523

  Multiplying only · CPC title

• G06F17/153

  Multidimensional correlation or convolution · CPC title