Method for manufacturing reformed sic wafer, epitaxial layer-attached sic wafer, method for manufacturing same, and surface treatment method

Patent metadata

Field	Value
Publication number	US-11261539-B2
Application number	US-201816495282-A
Country	US
Kind code	B2
Filing date	Mar 20, 2018
Priority date	Mar 22, 2017
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

In a method for manufacturing a reformed SiC wafer 41 (a surface treatment method for a SiC wafer) having its surface that is reformed by processing an untreated SiC wafer 40 before formation of an epitaxial layer 42, the method includes a surface reforming step as described below. That is, the untreated SiC wafer 40 includes BPDs as dislocations parallel to an inside of a (0001) face, and TEDs. Property of the surface of the untreated SiC wafer 40 is changed so as to have higher rate in which portions having BPDs on the surface of the untreated SiC wafer 40 propagate as TEDs at a time of forming the epitaxial layer 42.

First claim

The invention claimed is:

1. A method for manufacturing a reformed SiC wafer having a surface that is reformed by processing an untreated SiC wafer that is an SiC wafer before formation of an epitaxial layer and that includes at least in a surface, thereof basal plane dislocations as dislocations parallel to an inside of a (0001) face, the method comprising:
a surface reforming step comprising forming {1-100} molecular layer steps on the surface of the untreated SiC wafer,
wherein the surface reforming step changes property of the surface of the untreated SiC wafer so that the basal plane dislocations on the surface of the untreated SiC wafer propagate as threading edge dislocations at a higher rate at a time of forming the epitaxial layer.

2. A method for manufacturing a reformed SiC wafer having a surface that is reformed by processing an untreated SiC wafer that is an SiC wafer before formation of an epitaxial layer and that includes at least in a surface, thereof basal plane dislocations as dislocations parallel to an inside of a (0001) face, the method comprising:
a surface reforming step that comprises reforming the surface of the untreated SiC wafer by forming {1-100} molecular layer steps on the surface of the untreated SiC wafer.

3. The method for manufacturing the reformed SiC wafer according to claim 2 , wherein
in the surface reforming step, the basal plane dislocations generated on the surface of the untreated SiC wafer are converted to threading edge dislocations.

4. The method for manufacturing the reformed SiC wafer according to claim 3 , wherein
the untreated SiC wafer is subjected to planarization during the surface reforming step.

5. The method for manufacturing the reformed SiC wafer according to claim 3 , wherein
performing the surface reforming step causes an arithmetic mean roughness (Ra) of the epitaxial layer formed on the surface of the reformed SiC wafer to be 1 nm or less.

6. The method for manufacturing the reformed SiC wafer according to claim 5 , wherein
in the surface reforming step, the untreated SiC wafer is heated under Si vapor pressure.

7. A method for manufacturing an epitaxial layer-formed SiC wafer comprising:
an epitaxial layer forming step of forming the epitaxial layer on the reformed SiC wafer manufactured by the method for manufacturing the reformed SiC wafer according to claim 1 .

8. The method for manufacturing the epitaxial layer-formed SiC wafer according to claim 7 , wherein
a conversion ratio (%) of basal plane dislocation to threading edge dislocation, that is realized by performing the surface reforming step with respect to the untreated SiC wafer to form {1-100} molecular layer steps, and by performing the epitaxial layer forming step with respect to the reformed SiC wafer to reduce the size of the basal plane dislocations at an initial stage of such formation of the epitaxial layer, is 5% or more higher than the conversion ratio (%) when the epitaxial layer is formed after performing chemical mechanical polishing with respect to the untreated SiC wafer.

9. An epitaxial layer-formed SiC wafer comprising:
an SiC wafer; and
an epitaxial layer formed on the SiC wafer, wherein the surface of the SiC wafer includes basal plane dislocations as dislocations parallel to an inside of a (0001) face,
density of the basal plane dislocation on the surface of the epitaxial layer is 5% or less of density of the basal plane dislocation on the surface of the SiC wafer, and
{1-100} molecular layer steps are formed on the surface of the SiC wafer:.

10. The epitaxial layer-formed SiC wafer according to claim 9 , wherein
an arithmetic mean roughness (Ra) on the surface of the epitaxial layer of the SiC wafer is 1 nm or less.

11. The epitaxial layer-formed SiC wafer according to claim 9 , wherein
a conversion ratio (%) as a ratio in which the basal plane dislocations on the surface of the SiC wafer are converted to threading edge dislocations in the epitaxial layer, is 5% or more higher than the conversion ratio (%) when the epitaxial layer is formed after performing chemical mechanical polishing with respect to the SiC wafer.

12. The epitaxial layer-formed SiC wafer according to claim 9 , wherein
only one epitaxial layer is formed on the SiC wafer,
density of the basal plane dislocation on the surface of the epitaxial layer is 5% or less of density of the basal plane dislocation on the surface of the SiC wafer.

Assignees

• Toyo Tanso Co

Inventors

• Torimi Satoshi
• Sudo Yusuke
• Shinohara Masato
• Teramoto Youji
• Sakaguchi Takuya
• Nogami Satoru
• Kitabatake Makoto

Classifications

• H10P14/3408

  Silicon carbide · CPC title

• H10P14/2925

  Surface structures · CPC title

• H10P14/2904 Primary

  Silicon carbide · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/2926

  Crystal orientations · CPC title