GaN-based VCSEL chip based on porous DBR and manufacturing method of the same

Patent metadata

Field	Value
Publication number	US-11258231-B2
Application number	US-201716500035-A
Country	US
Kind code	B2
Filing date	Jun 1, 2017
Priority date	Apr 6, 2017
Publication date	Feb 22, 2022
Grant date	Feb 22, 2022

Abstract

A GaN-based VCSEL chip based on porous DBR and a manufacturing method of the same, wherein the chip includes: a substrate; a buffer layer formed on the substrate; a bottom porous DBR layer formed on the buffer layer; an n-type doped GaN layer formed on the bottom porous DBR layer, which is etched downward on its periphery to form a mesa; an active layer formed on the n-type doped GaN layer; an electron blocking layer formed on the active layer; a p-type doped GaN layer formed on the electron blocking layer; a current limiting layer formed on the p-type doped GaN layer with a current window formed at a center thereof, wherein the current limiting layer covers sidewalls of the active layer, the electron blocking layer and the convex portion of the n-type doped GaN layer; a transparent electrode formed on the p-type doped GaN layer; an n-electrode formed on the mesa of the n-type doped GaN layer; a p-electrode formed on the transparent electrode with a recess formed therein; and a dielectric DBR layer formed on the transparent electrode in the recess of the p-electrode.

First claim

We claim:

1. A method for manufacturing a GaN-based VCSEL chip based on porous DBR, comprising:
step 1: growing a buffer layer, alternately stacked lightly doped layers and heavily doped layers, an n-type doped GaN layer, an active layer, an electron blocking layer, and a p-type doped GaN layer on a substrate sequentially, wherein the substrate is made of sapphire, Si or SiC;
step 2: performing lateral etching on the alternately stacked lightly doped layers and heavily doped layers by using an electrochemical etching method, so as to transform them to a bottom porous DBR layer in which porous layers and non-porous layers are alternately stacked;
step 3: etching down on a periphery of the p-type doped GaN layer by a depth so that a portion of the n-type doped GaN layer is etched, so as to form a mesa on the periphery of the n-type doped GaN layer;
step 4: forming a current limiting layer on sidewalls of the p-type doped GaN layer, the mesa, the active layer, and the electron blocking layer;
step 5: forming a current window on the current limiting layer, and removing a portion of the current limiting layer on the mesa, using a photolithography and etching technique;
step 6: forming a transparent electrode at the current window on the p-type doped GaN layer;
step 7: forming an n-electrode and a p-electrode on the mesa on which a portion of the current limiting layer is removed and a periphery of the transparent electrode respectively, wherein a recess is formed in a middle of the p-electrode; and
step 8: forming a dielectric DBR layer on an upper surface of the transparent electrode in the recess of the p-electrode, so as to complete the manufacturing.

2. The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 1 , wherein the dielectric DBR layer and the bottom porous DBR layer constitute upper and lower mirrors of the VCSEL chip respectively, and the bottom porous DBR layer has a reflectivity of above 95% at a peak wavelength of the active layer, which is higher than the reflectivity of the dielectric DBR layer.

3. The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 1 , wherein the bottom porous DBR layer has a material of a multi-periodic DBR formed by stacking porous nitride layers and non-porous nitride layers alternately.

4. The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 1 , wherein the current limiting layer is made of SiO 2 , SiNX, HfO 2 or Al 2 O 3 .

5. The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 1 , wherein an n-type GaN layer is further grown between the bottom porous DBR layer and the buffer layer, and is used as a current spreading layer applied for electrochemical etching to form the bottom porous DBR layer.

6. The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 1 , wherein the lightly doped layers have a doping concentration of 5×10 16 cm −3 and the heavily doped layers have a doping concentration of 1×10 19 cm −3 .

Assignees

• Inst Semiconductors Cas

Inventors

• Zhao Lixia
• Yang Chao
• Liu Lei
• Li Jing
• Wang Kaiyou
• Chen Hongda

Classifications

• H01S5/04257

  having positive and negative electrodes on the same side of the substrate · CPC title

• H01S5/3054

  p-doping · CPC title

• H01S5/187

  using Bragg reflection · CPC title

• H01S5/18361 Primary

  Structure of the reflectors, e.g. hybrid mirrors · CPC title

• H01S5/2009

  by using electron barrier layers · CPC title