Thin film transistor and manufacturing method thereof, and display apparatus

Patent metadata

Field	Value
Publication number	US-11257954-B2
Application number	US-201916959179-A
Country	US
Kind code	B2
Filing date	Nov 19, 2019
Priority date	Jan 9, 2019
Publication date	Feb 22, 2022
Grant date	Feb 22, 2022

Abstract

Provided are a thin film transistor including: a base cushion layer having a recessed portion, base insulating layer, source-drain layer and active layer. The base insulating layer is located on a side of the base cushion layer where the recessed portion is located, and has a first and second partition walls that are spaced apart, and an orthographic projection region of a gap region between the first and second partition walls onto the base cushion layer is located at a region where the recessed portion is located; and both orthographic projection regions of the first and second partition walls onto the base cushion layer partially overlap with the recessed portion region; and both the source-drain layer and the active layer are located on the side of the base insulating layer away from the base cushion layer.

First claim

What is claimed is:

1. A thin film transistor, comprising: a base cushion layer, a base insulating layer, a source-drain layer, an active layer, a second gate layer and a first gate insulating layer, wherein
the basic cushion layer has a recessed portion;
the base insulating layer is located on a side of the base cushion layer where an opening of the recessed portion is located; the base insulating layer has, on a side of the base insulating layer away from the base cushion layer, a first partition wall and a second partition wall that are and protruded in a direction away from the base cushion layer and spaced apart, and an orthographic projection region of a gap region between the first partition wall and the second partition wall onto the base cushion layer is located at a region where the recessed portion is located; and both orthographic projection regions of the first partition wall and the second partition wall onto the base cushion layer partially overlap with the region where the recessed portion is located;
both the source-drain layer and the active layer are located on the side of the base insulating layer away from the base cushion layer, and arranged sequentially along a direction away from the base cushion layer; and
both the second gate layer and the first gate insulating layer are located on a side of the active layer away from the basic cushion layer, and the first gate insulating layer is located between the active layer and the second gate layer.

2. The thin film transistor according to claim 1 , wherein the base cushion layer comprises: a first cushion block and a second cushion block that are spaced apart, and the recessed portion is located between the first cushion block and the second cushion block.

3. The thin film transistor according to claim 1 , wherein a recession depth of the recessed portion ranges from 5 nm to 50 μm; and
a width of the recessed portion ranges from 5 nm to 50 μm in an arrangement direction of a source and a drain in the source-drain layer.

4. The thin film transistor according to claim 1 , wherein a spacing between the source and the drain in the source-drain layer ranges from 1 nm to 5 μm.

5. The thin film transistor according to claim 1 , wherein a material of the basic cushion layer comprises a conductive material, and the basic cushion layer serves as a first gate layer in the thin film transistor.

6. The thin film transistor according to claim 1 , wherein the thin film transistor further comprises: a third gate layer and a second gate insulating layer that are located on the side of the basic cushion layer away from the basic insulating layer, and the second gate insulating layer is located between the active layer and the third gate layer.

7. The thin film transistor according to claim 1 , wherein the base cushion layer comprises: a substrate, as well as a first bump and a second bump that are spaced apart and located on one side of the substrate, and the recessed portion is located between the first bump and the second bump.

8. A method for manufacturing a thin film transistor the method comprising:
forming a base cushion layer having a recessed portion;
depositing a base insulating layer on a side of the base cushion layer where an opening of the recessed portion is located, wherein the base insulating layer has, on a side of the base insulating layer away from the base cushion layer, a first partition wall and a second partition wall that are and protruded in a direction away from the base cushion layer and spaced apart, and an orthographic projection region of a gap region between the first partition wall and the second partition wall onto the base cushion layer is within a region where the recessed portion is located; and both orthographic projection regions of the first partition wall and the second partition wall onto the base cushion layer partially overlap with the region where the recessed portion is located;
depositing a source-drain layer on the side of the base insulating layer away from the base cushion layer,
forming an active layer on a side of the source-drain layer away from the base cushion layer;
forming a first gate insulating layer on a side of the active layer away from the base cushion layer; and
forming a second gate layer on a side of the first gate insulating layer away from the base cushion layer.

9. The method according to claim 8 , wherein forming the active layer on the side of the source-drain layer away from the base cushion layer comprises:
depositing the active layer on the side of the source-drain layer away from the base cushion layer.

10. The method according to claim 8 , wherein forming the base cushion layer having the recessed portion comprises:
forming a base material layer; and
treating the base material layer with a photoetching technology to obtain the base cushion layer.

11. The method according to claim 8 , wherein a material of the base cushion layer comprises a conductive material, the base cushion layer being a first gate layer in the thin film transistor.

12. The method according to claim 8 , wherein before forming the base cushion layer having the recessed portion, the method further comprises:
forming a third gate layer and a second gate insulating layer that are stacked, and
forming the base cushion layer having the recessed portion comprises:
forming the base cushion layer on a side of the second gate insulating layer away from the third gate layer.

13. A display apparatus, comprising a thin film transistor, and the thin film transistor comprising: a base cushion layer, a base insulating layer, a source-drain layer, an active layer, a second gate layer and a first gate insulating layer, wherein
the basic cushion layer has a recessed portion;
the base insulating layer is located on a side of the base cushion layer where an opening of the recessed portion is located; the base insulating layer has, on a side of the base insulating layer away from the base cushion layer, a first partition wall and a second partition wall that are and protruded in a direction away from the base cushion layer and spaced apart, and an orthographic projection region of a gag region between the first partition wall and the second partition wall onto the base cushion layer is located at a region where the recessed portion is located; and both orthographic projection regions of the first partition wall and the second partition wall onto the base cushion layer partially overlap with the region where the recessed portion is located;
both the source-drain layer and the active layer are located on the side of the base insulating layer away from the base cushion layer, and arranged sequentially along a direction away from the base cushion layer; and
both the second gate layer and the first gate insulating layer are located on a side of the active layer away from the basic cushion layer, and the first gate insulating layer is located between the active layer and the second gate layer.

14. The display apparatus according to claim 13 , wherein the base cushion layer comprises: a first cushion block and a second cushion block that are spaced apart, and the recessed portion is located between the first cushion block and the second cushion block.

15. The display apparatus according to claim 13 , wherein the base cushion layer comprises: a substrate, as well as a first bump and a second bump that are spaced apart and located on one side of the substrate, and the recessed portion is located between the first bump and the second bump.

16. The display apparatus according to claim 13 , wherein a recession depth of

Assignees

• Boe Technology Group Co Ltd

Inventors

• Ma Xiaochen
• Yuan Guangcai
• Ning ce
• Gu Xin
• Hu hehe

Classifications

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10D30/6758 Primary

  characterised by the insulating substrates · CPC title

• H10D64/27

  Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates · CPC title