Semiconductor package with integrated passive electrical component

Patent metadata

Field	Value
Publication number	US-11257739-B2
Application number	US-202016927694-A
Country	US
Kind code	B2
Filing date	Jul 13, 2020
Priority date	Nov 22, 2017
Publication date	Feb 22, 2022
Grant date	Feb 22, 2022

Abstract

A method includes forming a first magnetic material on a first surface of a conductive loop, forming a second magnetic material on a second surface of the conductive loop opposite the first surface to form an inductor, attaching a semiconductor die to a leadframe, and attaching the inductor to the leadframe with solder balls. The semiconductor die is between the inductor and the leadframe. The conductive loop: spans parallel to the leadframe; or is between the first magnetic material and the second magnetic material.

First claim

What is claimed is:

1. A method, comprising:
forming a first magnetic material on a first surface of a conductive loop;
forming a second magnetic material on a second surface of the conductive loop opposite the first surface to form an inductor;
attaching a semiconductor die to a leadframe; and
attaching the inductor to the leadframe with solder balls, in which the semiconductor die is between the inductor and the leadframe, and the conductive loop: spans parallel to the leadframe; or is between the first magnetic material and the second magnetic material.

2. The method of claim 1 , wherein forming the first and second magnetic materials comprises applying a magnetic mold compound to the first and second surfaces of the conductive loop.

3. The method of claim 1 , wherein forming the first and second magnetic materials comprises attaching a magnetic sheet to the first surface of the conductive loop and attaching another magnetic sheet to the second surface of the conductive loop.

4. The method of claim 1 , further comprising encapsulating the inductor and semiconductor die in mold compound.

Assignees

• Texas Instruments Inc

Inventors

• Mullenix Joyce Marie
• Massolini Roberto Giampiero
• Joshi Rajeev D

Classifications

• H10W90/738

  between a chip and a stacked discrete passive device · CPC title

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W72/354

  comprising polymers · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title