Apparatus for testing electronic devices

Patent metadata

Field	Value
Publication number	US-11255903-B2
Application number	US-202017036839-A
Country	US
Kind code	B2
Filing date	Sep 29, 2020
Priority date	Apr 27, 2005
Publication date	Feb 22, 2022
Grant date	Feb 22, 2022

Abstract

An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

First claim

What is claimed:

1. An apparatus for testing integrated circuits of devices, comprising:
at least one frame;
a holder for the device, secured to the frame;
a support structure held by the frame;
a plurality of terminals held by the support structure, the holder and support structure being movable relative to one another so that each one of the terminals releasably makes contact with a respective contact of the device;
a power source;
a power electrical path connecting the power source to a power terminal of the terminals held by the support structure;
a signal source; and
a plurality of signal electrical paths, each connecting the signal source to a respective signal terminal of the terminals held by the support structure.

2. An apparatus for testing an integrated circuits on devices comprising:
a plurality of electrical subassemblies including a plurality of pattern generator, driver, and power boards divided into physical zones with each physical zone including one pattern generator board, at least one driver board, and at least one power board connected to one another; and
a configuration file having information representing flow of current through the electrical subassemblies connected to one another in an interconnection scheme,
wherein the electrical subassemblies are organized into at least one logical zone, and wherein the logical zone comprises a plurality of pattern generators.

3. The apparatus of claim 2 , wherein the electrical subassemblies are organized into a plurality of logical zones, and wherein one or more of the logical zones comprises a plurality of pattern generators.

4. The apparatus of claim 2 , wherein the at least one logical zone is divided into a plurality of the physical zones.

5. The apparatus of claim 4 , wherein the configuration file has a zone name field indicating a plurality of respective ones of the physical zones.

6. The apparatus of claim 5 , wherein physical zones having the same zone name field are grouped into a logical zone.

7. The apparatus of claim 2 , wherein the electrical subassemblies in the logical zone are of the same type and run the same test program at the same time.

8. The apparatus of claim 3 , wherein the electrical subassemblies in each of the plurality of logical zones are of the same type and run the same test program at the same time, and wherein each of the plurality of logical zones runs a different test program at the same time.

9. A method for testing integrated circuits on devices comprising:
running more than one test program on the device simultaneously.

10. The method of claim 9 , wherein running more than one test program on the device simultaneously comprises:
providing a plurality of electrical subassemblies including a plurality of pattern generator, driver, and power boards divided into physical zones with each physical zone including one pattern generator board, at least one driver board, and at least one power board connected to one another, the electrical subassemblies are organized into at least one logical zone, and wherein the logical zone comprises a plurality of pattern generators;
providing a configuration file having information representing flow of current through the electrical subassemblies connected to one another in an interconnection scheme; and
running a test program through the at least one logical zone.

11. The method of claim 9 , wherein running more than one test program on the device simultaneously comprises:
providing a plurality of electrical subassemblies including a plurality of pattern generator, driver, and power boards divided into physical zones with each physical zone including one pattern generator board, at least one driver board, and at least one power board connected to one another, the electrical subassemblies are organized into a plurality of logical zones, and wherein each of the logical zones comprises a plurality of pattern generators;
providing a configuration file having information representing flow of current through the electrical subassemblies connected to one another in an interconnection scheme; and
running a test program through each of the logical zones simultaneously.

Assignees

• Aehr Test Systems

Inventors

• Richmond Ii Donald P
• Deboe Kenneth W
• Uher Frank O
• Jovanovic Jovan
• Lindsey Scott E
• Maenner Thomas T
• Shepherd Patrick M
• Tyson Jeffrey L
• Carbone Mark C
• Burke Paul W
• Cao Doan D
• Tomic James F
• Vu Long V

Classifications

• H10P74/00 Primary

  Testing or measuring during manufacture or treatment of wafers, substrates or devices · CPC title

• G01R31/2889

  Interfaces, e.g. between probe and tester (G01R31/31905 and G01R1/07364 take precedence) · CPC title

• G01R31/2855

  Environmental, reliability or burn-in testing · CPC title

• G01R31/2877

  related to cooling · CPC title

• G01R31/2642

  Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests · CPC title