Processing apparatus, image device and system with image data via single common data bus

Patent metadata

Field	Value
Publication number	US-11252305-B2
Application number	US-201716094350-A
Country	US
Kind code	B2
Filing date	Apr 10, 2017
Priority date	May 27, 2016
Publication date	Feb 15, 2022
Grant date	Feb 15, 2022

Abstract

Provided is a processing apparatus including a processing unit that is connectable to a data bus, and performs output control on respective images captured by a plurality of image sensors connected to the data bus during a predetermined period of time. A timing of output of the image performed by each of the plurality of image sensors is changed by the output control.

First claim

The invention claimed is:

1. A processing apparatus comprising:
a processing circuitry configured to
send respective timing control outputs to a plurality of image sensors via one or more control buses, and
receive respective images from the plurality of image sensors via a single common data bus based on the respective timing control outputs that are sent to the plurality of image sensors, the single common data bus being different than the one or more control buses,

wherein one or more image sensors of the plurality of image sensors are individually configured to capture one image of the respective images by performing a global shutter method,
wherein the one or more image sensors individually include a holding capacitance that is configured to temporarily hold the one image of the respective images, and
wherein each image sensor of the plurality of image sensors includes an array of pixels.

2. The processing apparatus according to claim 1 , wherein
each timing control output of the respective timing control outputs includes a timing that delays an output of an image from each image sensor of the plurality of image sensors.

3. The processing apparatus according to claim 1 , wherein
each timing control output of the respective timing control outputs includes a plurality of timings that are output at intervals at which packets of an image from each image sensor of the plurality of image sensors are output.

4. The processing apparatus according to claim 1 , wherein
the processing circuitry is further configured to perform time-division multiplexing of the respective images from the plurality of image sensors with the respective timing control outputs.

5. The processing apparatus according to claim 4 , wherein
the processing circuitry is further configured to control each of the plurality of image sensors to record one of the respective timing control outputs in a register.

6. The processing apparatus according to claim 1 , wherein
the respective images captured by the plurality of image sensors are captured substantially at the same time.

7. The processing apparatus according to claim 1 , wherein
each image of the respective images includes image data based on all pixel signals from a corresponding array of pixels of the plurality of image sensors.

8. An image device comprising:
an image sensor configured to
capture an image by performing a global shutter method,
temporarily hold the image with a holding capacitance,
receive a timing control output via a control bus, and
output the image that is captured via a single common data bus based on the timing control output, the single common data bus being different than the control bus, and the single common data bus being shared with other image sensors,
wherein, to capture the image by performing the global shutter method, the image sensor is further configured to capture the image by performing the global shutter method on an array of pixels.

9. The image device according to claim 8 , wherein
the timing control output includes a timing that delays the output of the image that is captured.

10. The image device according to claim 8 , wherein
the timing control output includes timings that are output intervals at which packets of the image that is captured are output.

11. The image device according to claim 8 , wherein
the image sensor further includes a register, and
responsive to receiving the timing control output, the image sensor is further configured to store the timing control output in the register.

12. The image device according to claim 8 , wherein
the image includes image data based on all pixels signals output from the array of pixels.

13. A system comprising:
a single common data bus;
one or more control buses that are different than the single common data bus;
a plurality of image sensors that are connected to the single common data bus and the one or more control buses, each of the plurality of image sensors are configured to capture an image; and
a processing circuitry that is connected to the single common data bus and the one or more control buses, the processing circuitry is configured to send respective timing control outputs to the plurality of image sensors via the one or more control buses, wherein
the plurality of image sensors are configured to receive the respective timing control outputs from the processing circuitry, and output respective images that are captured to the processing circuitry via the single common data bus based on the respective timing control outputs that are received,
one or more image sensors of the plurality of image sensors are individually configured to capture one of the respective images by performing a global shutter method,
the one or more image sensors individually include a holding capacitance that is configured to temporarily hold the one of the respective images, and
each image sensor of the plurality of image sensors includes an array of pixels.

14. The system according to claim 13 , wherein
each timing control output of the respective timing control outputs includes a timing that delays an output of the image from the each of the plurality of image sensors.

15. The system according to claim 13 , wherein
each timing control output of the respective timing control outputs includes a plurality of timings that are output at intervals at which packets of the image from the each of the plurality of image sensors are output.

16. The system according to claim 13 , wherein
the processing circuitry is further configured to perform time-division multiplexing of the respective images from the plurality of image sensors with the respective timing control outputs.

17. The system according to claim 13 , wherein
the processing circuitry is further configured to control each of the plurality of image sensors to record one of the respective timing control outputs in a register.

18. The system according to claim 13 , wherein
the respective images captured by the plurality of image sensors are captured substantially at the same time.

19. The system according to claim 13 , wherein
each of the respective images includes image data based on all pixel signals from a corresponding array of pixels of the plurality of image sensors.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Mitsubayashi Hideki
• Yokokawa Takashi
• Yoshimochi Naoki

Classifications

• H04N23/60

  Control of cameras or camera modules · CPC title

• H04N23/90

  Arrangement of cameras or camera modules, e.g. multiple cameras in TV studios or sports stadiums · CPC title

• H04N5/0733 Primary

  for distributing synchronisation pulses to different TV cameras · CPC title

• H04N7/181

  for receiving images from a plurality of remote sources · CPC title

• H04N7/18

  Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast · CPC title