Slew rate control circuit for an image sensor

Patent metadata

Field	Value
Publication number	US-11070754-B1
Application number	US-202016828423-A
Country	US
Kind code	B1
Filing date	Mar 24, 2020
Priority date	Mar 24, 2020
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

In an embodiment, an image sensor includes: first and second voltage rails; first and second regulators configured to generate first and second regulated voltage at the first and second voltage rails, respectively; and a plurality of pixels coupled to the first and second voltage rails. Each pixel includes: first and second transistor coupled first and second storage capacitor, respectively. A third transistor is coupled between a control terminal of the first transistor and the first or second voltage rails. The third transistor is configured to limit a slew rate of current flowing between the control terminal of the second transistor and the first or second voltage rails to a first slew rate when the image sensor operates in global shutter mode, and to a second slew rate when the image sensor operates in rolling mode, the first slew rate being smaller than the second slew rate.

First claim

What is claimed is:

1. An image sensor comprising:
first and second voltage rails;
a first regulator having an output coupled to the first voltage rail and configured to generate a first regulated voltage;
a second regulator having an output coupled to the second voltage rail and configured to generate a second regulated voltage lower than the first regulated voltage; and
a plurality of pixels coupled to the first and second voltage rails, wherein each pixel of the plurality of pixels comprises:
first and second storage capacitors,
a first transistor having a current path coupled to the first storage capacitor,
a second transistor having a current path coupled to the second storage capacitor, and
a third transistor coupled between a control terminal of the first transistor and the first or second voltage rails, wherein the third transistor is configured to limit a slew rate of current flowing between the control terminal of the second transistor and the first or second voltage rails to a first slew rate when the image sensor operates in global shutter mode, and to a second slew rate when the image sensor operates in rolling mode, the first slew rate being smaller than the second slew rate.

2. The image sensor of claim 1 , wherein the third transistor is configured to limit the slew rate of current between the control terminal of the second transistor and the first or second voltage rails to the first slew rate only during a transition of the first or second transistors from a first state to a second state.

3. The image sensor of claim 2 , wherein the first state is high and corresponds to the first regulated voltage, and wherein the second state is low and corresponds to the second regulated voltage.

4. The image sensor of claim 1 , wherein the third transistor is coupled between the control terminal of the second transistor and the second voltage rail.

5. The image sensor of claim 1 , wherein each pixel further comprises a fourth transistor coupled between a control terminal of the first transistor and the first or second voltage rails, wherein the fourth transistor is configured to limit a slew rate of current flowing between the control terminal of the first transistor and the first or second voltage rails to the first slew rate when the image sensor operates in global shutter mode, and to the second slew rate when the image sensor operates in rolling mode, the first slew rate being smaller than the second slew rate.

6. The image sensor of claim 1 , wherein an aggregated capacitance of control terminals of each of the second transistors of activated pixels of the plurality of pixels is at least 100 times larger during global shutter mode than during rolling mode.

7. The image sensor of claim 1 , wherein an aggregated capacitance of control terminals of each of the second transistors of activated pixels of the plurality of pixels during global shutter mode is at least 50 times larger than a capacitance associated with the first or second voltage rail.

8. The image sensor of claim 1 , wherein each pixel further comprises a first current mirror comprising the third transistor and a fourth transistor.

9. The image sensor of claim 8 , wherein the first current mirror has a ratio of M:1, wherein M is a positive integer greater than 1.

10. The image sensor of claim 9 , wherein M is 100.

11. The image sensor of claim 8 , each pixel further comprises a second current mirror coupled between the control terminal of the second transistor and the first or second voltage rails, wherein the first current mirror is disabled during rolling mode, and wherein the second current mirror is disabled during global shutter mode.

12. The image sensor of claim 11 , wherein the second current mirror has a 1:1 ratio.

13. The image sensor of claim 11 , wherein the third transistor is coupled between the control terminal of the second transistor and the second voltage rail, and wherein each pixel further comprises:
a first switch coupled between the second voltage rail and a control terminal of the third transistor; and
a second switch coupled between the second voltage rail and the second current mirror, wherein the first switch is configured to turn on during rolling mode, and wherein the second switch is configured to turn on during global shutter mode.

14. The image sensor of claim 1 , wherein each pixel further comprises a pinned photodiode.

15. The image sensor of claim 14 , wherein each pixel further comprises a fourth transistor having a control terminal coupled to the pinned photodiode, and a current patch coupled to a current path of the first transistor.

16. A method comprising:
generating a first voltage at a first voltage rail that is coupled to a plurality of pixels of an image sensor;
generating a second voltage at a second voltage rail that is coupled to the plurality of pixels, wherein the second voltage is different than the first voltage;
transitioning a first signal at a control terminal of a first transistor from the first voltage to the second voltage, wherein the first transistor has a current path coupled to a first storage capacitor;
after transitioning the first signal from the first voltage to the second voltage, transitioning a second signal at a control terminal of a second transistor from the first voltage to the second voltage, wherein the second transistor has a current path coupled to a second storage capacitor;
after transitioning the second signal from the first voltage to the second voltage, transitioning the second signal from the second voltage to the first voltage; and
during the transition of the second signal from the second voltage to the first voltage, limit a slew rate of a current flowing between the control terminal of the first or second transistor and the first voltage rail to a first slew rate when the image sensor is in global shutter mode, and to a second slew rate when the image sensor is in rolling mode, wherein the first slew rate is smaller than the second slew rate.

17. The method of claim 16 , wherein the first voltage is about 0.4 V and the second voltage is about 3.3 V.

18. The method of claim 16 , further comprising, after transitioning the second signal from the second voltage to the first voltage, transitioning the first signal from the second voltage to the first voltage.

19. An integrated circuit comprising:
a first internal LDO configured to generate a first regulated voltage at a first voltage rail, wherein the first internal LDO is not coupled to a compensation capacitor external to the integrated circuit;
a second internal LDO configured to generate a second regulated voltage at a second voltage rail, wherein the second internal LDO is not coupled to a compensation capacitor external to the integrated circuit, and wherein the second regulated voltage is lower than the first regulated voltage; and
an image sensor comprising a plurality of image sensor pixels arranged in rows and columns and coupled to the first and second voltage rails, wherein each image sensor pixel of the plurality of image sensor pixels comprises:
first and second storage capacitors,
a first transistor having a current path coupled to the first storage capacitor,
a second transistor having a current path coupled to the second storage capacitor, and
a third transistor coupled between a control terminal of the first transistor and the second voltage rail, wherein the third transistor is configured to limit a slew rate of current flowing between the control terminal of the first transistor and the second voltage

Assignees

• St Microelectronics Asia Pacific Pte Ltd
• St Microelectronics Alps Sas

Inventors

• Zhang Hongliang
• Chua Lookah
• Mas Celine
• Hnin Wai Yin

Classifications

• H04N25/617 Primary

  for reducing electromagnetic interference, e.g. clocking noise · CPC title

• H04N25/76 Primary

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H04N25/626 Primary

  Reduction of noise due to residual charges remaining after image readout, e.g. to remove ghost images or afterimages · CPC title

• H04N25/709

  Circuitry for control of the power supply · CPC title

• H10F39/8037

  the integrated elements comprising a transistor · CPC title