Apparatus for compensating for radiation resistance of semiconductor memory, method therefor, and electronic circuit

Patent metadata

Field	Value
Publication number	US-11250906-B2
Application number	US-201917057428-A
Country	US
Kind code	B2
Filing date	Oct 11, 2019
Priority date	Oct 19, 2018
Publication date	Feb 15, 2022
Grant date	Feb 15, 2022

Abstract

The purpose of the invention is to compensate for the radiation tolerance of a semiconductor memory. An apparatus ( 10 ) for compensating for radiation tolerance comprises: a voltage value acquisition unit ( 11 ) that acquires a data retention voltage value that is a maximum voltage value at which data is inverted when a power supply voltage of a semiconductor memory having a latch circuit is lowered; a correction value determination unit ( 12 ) that determines a voltage correction value on the basis of a difference between the data retention voltage value and a reference voltage value; and a voltage adjustment unit ( 13 ) that adjusts at least one among the power supply voltage and a substrate bias voltage by using the voltage correction value. The reference voltage value is set to be equal to or lower than the data retention voltage value that satisfies a required radiation tolerance.

First claim

The invention claimed is:

1. An apparatus for compensating for radiation tolerance of a semiconductor memory having a latch circuit, the apparatus comprising:
a voltage value acquisition unit that acquires a data retention voltage value, the data retention voltage value corresponding to a maximum voltage value at which data is inverted, when a power supply voltage of the semiconductor memory is lowered;
a correction value determination unit that determines a voltage correction value based on a difference between the data retention voltage value and a reference voltage value; and
a voltage adjustment unit that adjusts at least one of the power supply voltage and a substrate bias voltage using the voltage correction value,
wherein the reference voltage value is set to be equal to or lower than the data retention voltage value of a semiconductor memory that satisfies required radiation tolerance.

2. The apparatus for compensating for radiation tolerance of a semiconductor memory according to claim 1 ,
wherein the voltage value acquisition unit acquires the data retention voltage value for each of a plurality of the semiconductor memories,
the correction value determination unit determines the voltage correction value for each semiconductor memory based on a difference between the data retention voltage value acquired for each semiconductor memory and the reference voltage value that is a common value among the semiconductor memories, and
the voltage adjustment unit adjusts at least one of the power supply voltage of the semiconductor memory and the substrate bias voltage using the voltage correction value determined for each semiconductor memory.

3. The apparatus for compensating for radiation tolerance of a semiconductor memory according to claim 1 ,
wherein the semiconductor memory is mounted with a plurality of the latch circuits,
the voltage value acquisition unit acquires data retention voltage values of a part or all of the plurality of the latch circuits, and
the correction value determination unit calculates a feature value of the data retention voltage values by statistically processing a plurality of the data retention voltage values acquired by the voltage value acquisition unit and determines the voltage correction value based on a difference between the calculated feature value of the data retention voltage values and the reference voltage value.

4. An electronic circuit comprising:
the apparatus for compensating for radiation tolerance of a semiconductor memory according to claim 1 ; and
the semiconductor memory.

5. A method for compensating for radiation tolerance of a semiconductor memory having a latch circuit, the method comprising:
a voltage value acquisition step of acquiring a data retention voltage value, the data retention voltage value corresponding to a maximum voltage at which data is inverted, when a power supply voltage of the semiconductor memory is lowered;
a correction value determination step of determining a voltage correction value based on a difference between the data retention voltage value and a reference voltage value; and
a voltage adjustment step of adjusting at least one of the power supply voltage and a substrate bias voltage using the voltage correction value,
wherein the reference voltage value is set to be equal to or lower than the data retention voltage value of a semiconductor memory that satisfies required radiation tolerance.

6. The method for compensating for radiation tolerance of a semiconductor memory according to claim 5 ,
wherein, in the voltage value acquisition step, the data retention voltage value is acquired for each of a plurality of the semiconductor memories,
in the correction value determination step, the voltage correction value is determined for each semiconductor memory based on a difference between the data retention voltage value acquired for each semiconductor memory and the reference voltage value that is a common value among the semiconductor memories, and
in the voltage adjustment step, at least one of the power supply voltage of each semiconductor memory and the substrate bias voltage is adjusted using the voltage correction value determined for each semiconductor memory.

7. The method for compensating for radiation tolerance of a semiconductor memory according to claim 5 ,
wherein the semiconductor memory is mounted with a plurality of the latch circuits,
in the voltage value acquisition step, data retention voltage values of a part or all of the plurality of the latch circuits are acquired, and
in the correction value determination step, a feature value of the data retention voltage values is calculated by statistically processing a plurality of the data retention voltage values acquired in the voltage value acquisition step and the voltage correction value is determined based on a difference between the calculated feature value of the data retention voltage values and the reference voltage value.

Assignees

• Mitsubishi Heavy Ind Ltd

Inventors

• Mori Yoshiharu
• KUSANO Masaki
• Matsuura Daisuke
• Kobayashi Daisuke
• Hirose Kazuyuki
• Kawasaki Osamu

Classifications

• G11C29/50016

  of retention · CPC title

• G11C2029/5004

  Voltage · CPC title

• G11C29/50004

  of threshold voltage · CPC title

• G11C11/417 Primary

  for memory cells of the field-effect type · CPC title

• G11C2029/0409

  Online test · CPC title