Cell structure of random access memory, random access memory and operation methods

Patent metadata

Field	Value
Publication number	US-2016111146-A1
Application number	US-201514772371-A
Country	US
Kind code	A1
Filing date	Apr 17, 2015
Priority date	Apr 17, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

The present disclosure provides a cell structure, a random access memory and operation methods. The cell structure with four transistors, including a first N-type transistor, a first P-type transistor, a second N-type transistor and a second P-type transistor, in which an absolute value of a threshold voltage of the first N-type transistor is greater than an absolute value of a threshold voltage of the second N-type transistor, and an absolute value of a threshold voltage of the first P-type transistor is greater than an absolute value of a threshold voltage of the second P-type transistor. The random access memory, including: two identical memory cell arrays including the cell structure with four transistors, a data write circuit and a data read circuit, by using Two Modular Redundancy harden method, and thus reading correctly and avoiding the mistake reversal caused by the single event upset effect.

First claim

1 . A cell structure of a random access memory, comprising: a first N-type transistor (N 1 ), a first P-type transistor (P 1 ), a second N-type transistor (NG 1 ) and a second P-type transistor (PG 1 ); wherein
a source electrode of the first N-type transistor (N 1 ) is connected to an adjustable low voltage (VSSI), a source electrode of the first P-type transistor (P 1 ) is connected to an adjustable high voltage (VDDI), a drain electrode of the first N-type transistor (N 1 ) is connected to a gate electrode of the first P-type transistor (P 1 ), a gate electrode of the first N-type transistor (N 1 ) is connected to a drain electrode of the first P-type transistor (P 1 ), a drain electrode of the second N-type transistor (NG 1 ) is connected to a bit line (BL), a gate electrode of the second N-type transistor (NG 1 ) is connected to a write word line (WWL), a source electrode of the second N-type transistor (NG 1 ) is connected to a first node (Q) between the gate electrode of the first N-type transistor (N 1 ) and the drain electrode of the first P-type transistor (P 1 ), a drain electrode of the second P-type transistor (PG 1 ) is connected to a complementary bit line (BLn), a gate electrode of the second P-type transistor (PG 1 ) is connected to a read word line (RWL), a source electrode of the second P-type transistor (PG 1 ) is connected to a second node (Qn) between the drain electrode of the first N-type transistor (N 1 ) and the gate electrode of the first P-type transistor (P 1 ).

2 . The cell structure according to claim 1 , wherein an absolute value of a threshold voltage of the first N-type transistor (N 1 ) is greater than an absolute value of a threshold voltage of the second N-type transistor (NG 1 ), and an absolute value of a threshold voltage of the first P-type transistor (P 1 ) is greater than an absolute value of a threshold voltage of the second P-type transistor (PG 1 ).

3 . The cell structure according to claim 1 , wherein a substrate of the first N-type transistor (N 1 ) and a substrate of the second N-type transistor (NG 1 ) are connected to a ground voltage (GND) respectively, and a substrate of the first P-type transistor (P 1 ) and a substrate of the second P-type transistor (PG 1 ) are connected to a power voltage (VDD) respectively.

4 . The cell structure according to claim 1 , wherein the adjustable low voltage (VSSI) is greater than or equal to the ground voltage (GND) and less than a half of the power voltage (VDD/2); the adjustable high voltage (VDDI) is less than or equal to the power voltage (VDD) and greater than the half of the power voltage (VDD/2).

5 . The cell structure according to claim 1 , wherein if the cell structure is in a maintain operation, the write word line (WWL) is maintained at a first low level, the read word line (RWL) is maintained at a first high level, the bit line (BL) is maintained at the first low level, the complementary bit line (BLn) is maintained at the first high level, the adjustable high voltage (VDDI) is maintained at a second high level, and the adjustable low voltage (VSSI) is maintained at a second low level, wherein the first high level is higher than the second high level, the first low level is lower than the second low level.

6 . The cell structure according to claim 1 , wherein if the cell structure is in a write operation comprising three phases of writing,
the write word line (WWL) is maintained at a first low level in a first phase of writing, and is maintained at a first high level in a second phase of writing and a third phase of writing; the read word line (RWL) is maintained at the first low level in the first phase of writing and the second phase of writing, and is maintained at the high level in the third phase of writing; the bit line (BL) is maintained at the first high level in the first phase of writing, the second phase of writing and the third phase of writing, if “1” is written, or the bit line (BL) is maintained at the first low level in the first phase of writing, the second phase of writing and the third phase of writing, if “0” is written; the complementary bit line (BLn) is maintained at the first high level in the first phase of writing, the second phase of writing and the third phase of writing; the adjustable high voltage (VDDI) is maintained at a second high level in the first phase of writing, the second phase of writing and the third phase of writing, wherein the first high level is higher than the second high level; and the adjustable low voltage (VS SI) is maintained at a second low level in the first phase of writing, and is maintained at the first low level in the second phase of writing and the third phase of writing, wherein the first low level is lower than the second low level.

7 . The cell structure according to claim 1 , wherein if the cell structure is in a read operation comprising two phases of reading,
the write word line (WWL) is maintained at a first low level in a first phase of reading and a second phase of reading; the read word line (RWL) is maintained at a first high level in the first phase of reading, and is maintained at the first low level in the second phase of reading; the bit line (BL) is maintained at the first low level in the first phase of reading and the second phase of reading; the complementary bit line (BLn) is maintained at the first high level in the first phase of reading and descended from the first high level to the first low level gradually in the second phase of reading, if “1” is read, or the complementary bit line (BLn) is maintained at the first high level in the first phase of reading and the second phase of reading if “0” is read; the adjustable high voltage (VDDI) is maintained at the first high level in the first phase of reading and the second phase of reading; and the adjustable low voltage (VS SI) is maintained at a second low level in the first phase of reading and the second phase of reading, wherein the first low level is lower than the second low level.

8 . The cell structure according to claim 1 , wherein if the cell structure is in a refresh operation,
the write word line (WWL) is maintained at a first voltage (Vthn), wherein the first voltage (Vthn) is a larger of the absolute value of the threshold voltage of the second N-type transistor (NG 1 ) and the absolute value of the threshold voltage of the first N-type transistor (N 1 ); the read word line (RWL) is maintained at a second voltage (VDD-|Vthp|), wherein the second voltage (VDD-|Vthp|) is a difference value of the power voltage (VDD) minus a third voltage (|Vthp|), wherein the third voltage (|Vthp|) is a larger of the absolute value of the threshold voltage of the second P-type transistor (PG 1 ) and the absolute value of the threshold voltage of the first P-type transistor (P 1 ); the bit line (BL) is maintained at a first low level; the complementary bit line (BLn) is maintained at a first high level; the adjustable high voltage (VDDI) is maintained at a second high level, wherein the first high level is higher than the second high level; the adjustable low voltage (VSSI) is maintained at a second low level, wherein the first low level is lower than the second low level.

9 . A random access memory, comprising two identical memory cell arrays, a data write circuit and a data read circuit; wherein
array structures of the two identical memory cell arrays are same, and same original stored information is stored in memory cells with a same address in the two identical memory cell arrays; the data write circuit is configured to write same data into the memory cells with the same address in the two identical memory cell arrays; the data read circuit is configured to select two pieces of stored informat

Assignees

• Univ Tsinghua
• Univ Tsinghua Graduate School

Inventors

• Pan Liyang
• Hong Xinhong
• Wu Dong

Classifications

• G11C11/4125

  Cells incorporating circuit means for protecting against loss of information · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C11/403

  with charge regeneration common to a multiplicity of memory cells, i.e. external refresh · CPC title

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G11C11/412

  using field-effect transistors only · CPC title