Shift register circuit, and driving method thereof, gate drive circuit and display device

Patent metadata

Field	Value
Publication number	US-11250750-B2
Application number	US-201816126032-A
Country	US
Kind code	B2
Filing date	Sep 10, 2018
Priority date	Nov 9, 2017
Publication date	Feb 15, 2022
Grant date	Feb 15, 2022

Abstract

A shift register circuit, a driving method thereof, a gate drive circuit and a display device are provided. The shift register circuit includes an input sub-circuit, an output sub-circuit, a discharge sub-circuit and a noise reduction sub-circuit. The input sub-circuit is connected to an input signal terminal, a first power source terminal and a pull-down node, and configured to, under the control of an input signal, output a first power source terminal signal to the pull-down node. In the shift register circuit, the discharge sub-circuit may control the potential of the pull-down node to be an ineffective potential at the input stage, thereby preventing the noise reduction sub-circuit from affecting the potentials of the pull-up node and the output terminal under the control of the pull-down node, and ensuring normal output of the shift register circuit.

First claim

What is claimed is:

1. A shift register circuit, comprising:
an input sub-circuit, an output sub-circuit, a discharge sub-circuit and a noise reduction sub-circuit; wherein
the input sub-circuit is connected to an input signal terminal, a first control signal terminal and a pull-up node respectively, and configured to, under the control of an input signal from the input signal terminal, output a first control signal from the first control signal terminal to the pull-up node;
the output sub-circuit is connected to a clock signal terminal, the pull-up node and an output terminal respectively, and configured to, under the control of the pull-up node, output a clock signal from the clock signal terminal to the output terminal;
the discharge sub-circuit is connected to the input signal terminal, a first power source terminal and a pull-down node respectively, and configured to, under the control of the input signal, output a first power source signal from the first power source terminal to the pull-down node; and
the noise reduction sub-circuit is connected to the pull-down node, the first power source terminal, the pull-up node and the output terminal respectively, and configured to, under the control of the pull-down node, output the first power source signal to the pull-up node and the output terminal respectively;
wherein the shift register circuit further comprises: a reset sub-circuit; wherein
the reset sub-circuit is connected to a reset signal terminal; a second control signal terminal and the pull-up node respectively, and configured to, under the control of a reset signal from the reset signal terminal, output a second control signal from the second control signal terminal to the pull-up node, wherein a potential of the second control signal is a second potential; and
the discharge sub-circuit is further connected to the reset signal terminal, and the discharge sub-circuit is further configured to, under the control of the reset signal, output the first power source signal to the pull-down node;

wherein the discharge sub-circuit comprises: a first transistor and a second transistor; wherein
a gate of the first transistor is connected to the input signal terminal, a first electrode of the first transistor is connected to the first power source terminal, and a second electrode of the first transistor is connected to the pull-down node; and
a gate of the second transistor is connected to the reset signal terminal, a first electrode of the second transistor is connected to the first power source terminal, and a second electrode of the second transistor is connected to the pull-down node;

wherein the noise reduction sub-circuit comprises: a ninth transistor and a tenth transistor; wherein
a gate of the ninth transistor is connected to the pull-down node, a first electrode of the ninth transistor is connected to the first power source terminal, and a second electrode of the ninth transistor is connected to the pull-up node; and
a gate of the tenth transistor is connected to the pull-down node, a first electrode of the tenth transistor is connected to the first power source terminal, and a second electrode of the tenth transistor is connected to the output terminal;

wherein the input sub-circuit comprises: a third transistor and a fourth transistor; and wherein the reset sub-circuit comprises: a fifth transistor and a sixth transistor; and the noise reduction sub-circuit further comprises: an eleventh transistor and a twelfth transistor; wherein
a gate of the eleventh transistor is connected to the pull-down node, a first electrode of the eleventh transistor is connected to the first power source terminal, and a second electrode of the eleventh transistor is connected to the second electrode of the third transistor and the first electrode of the fourth transistor respectively; and
a gate of the twelfth transistor is connected to the pull-down node, a first electrode of the twelfth transistor is connected to the first power source terminal, and a second electrode of the twelfth transistor is connected to the second electrode of the fifth transistor and the first electrode of the sixth transistor respectively; and

wherein a potential of the first control signal is a first potential, a potential of the first power source signal is a second potential, and a potential of the second control signal is the second potential.

2. The shift register circuit according to claim 1 , further comprising: a first pull-down control sub-circuit and a second pull-down sub-circuit; wherein
the first pull-down control sub-circuit is connected to the pull-down node and a second power source terminal, and configured to, under the control of a second power source signal from the second power source terminal, output the second power source signal to the pull-down node, wherein a potential of the second power source signal is a first potential; and
the second pull-down control sub-circuit is connected to the pull-up node, the pull-down node and the first power source terminal respectively, and configured to, under the control of the pull-up node, output the first power source signal from the first power source terminal to the pull-down node.

3. The shift register circuit according to claim 1 , wherein
a gate of the third transistor is connected to the input signal terminal, a first electrode of the third transistor is connected to the first control signal terminal, and a second electrode of the third transistor is connected to a first node; and
a gate of the fourth transistor is connected to the input signal terminal, a first electrode of the fourth transistor is connected to the first node, and a second electrode of the fourth transistor is connected to the pull-up node.

4. The shift register circuit according to claim 1 , wherein
a gate of the fifth transistor is connected to the reset signal terminal, a first electrode of the fifth transistor is connected to the second control signal terminal, and a second electrode of the fifth transistor is connected to a second node; and
a gate of the sixth transistor is connected to the reset signal terminal, a first electrode of the sixth transistor is connected to the second node, and a second electrode of the sixth transistor is connected to the pull-up node.

5. The shift register circuit according to claim 2 ; wherein the first pull-down control sub-circuit comprises: a seventh transistor; wherein
a gate and a first electrode of the seventh transistor are connected to the second power source terminal, and a second electrode of the seventh transistor is connected to the pull-down node.

6. The shift register circuit according to claim 2 , wherein the second pull-down control sub-circuit comprises: an eighth transistor; wherein
a gate of the eighth transistor is connected to the pull-up node, a first electrode of the eighth transistor is connected to the first power source terminal, and a second electrode of the eighth transistor is connected to the pull-down node.

7. The shift register circuit according to claim 1 , further comprising: a thirteenth transistor; wherein
a gate of the thirteenth transistor is connected to a general reset signal terminal, a first electrode of the thirteenth transistor is connected to the first power source terminal, and a second electrode of the thirteenth transistor is connected to the pull-up node.

8. The shift register circuit according to claim 7 , further comprising: a fourteenth transistor; wherein
a gate of the fourteenth transistor is connected to the general reset signal terminal, a first electrode of the fourteenth transistor is connected to the first power source terminal, and a second electrode of the fourteenth transistor is connected to the output terminal.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Zhichong
• Zheng Haoliang
• Han Seungwoo
• Shang Guangliang
• Han Mingfu
• Yuan Lijun
• Yao Xing

Classifications

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/3674

  Details of drivers for scan electrodes · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title