Gate drive circuit, array substrate, display panel and display device

Patent metadata

Field	Value
Publication number	US-9792851-B2
Application number	US-201514694954-A
Country	US
Kind code	B2
Filing date	Apr 23, 2015
Priority date	Dec 29, 2014
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

A gate drive circuit is disclosed. The gate drive circuit includes shift register units connected with gate lines. The gate drive circuit also includes clock signal lines to provide clock signals. A trigger signal terminal of the first shift register unit is connected with a first initial trigger signal line, and a trigger signal terminal of the p-th shift register unit is connected with an output terminal of the (p−1)-th shift register unit. An end signal terminal of the r-th shift register unit is connected with an output terminal of the (r+2 M-1 )-th shift register unit, low level signal terminals are connected with a first low level signal line, and reset signal terminals are connected with a reset signal line. In addition, forward scan signal terminals are connected with a first scan signal line, and backward scan signal terminals are connected with a second scan signal line.

First claim

What is claimed is:

1. A gate drive circuit, comprising:
N shift register units, each of which is connected with one of N gate lines of a display panel respectively; and
2 M clock signal lines configured to provide the N shift register units with clock signals, wherein each of the N shift register units is connected with exactly 2 M /2 clock signal lines,
wherein:
N is an even number, and M is a natural number larger than or equal to 2,
a trigger signal terminal of the first shift register unit is connected with a first initial trigger signal line, and a trigger signal terminal of the p-th shift register unit is connected with an output terminal of the (p−1)-th shift register unit, wherein p=2, 3, . . . , N,
an end signal terminal of the r-th shift register unit is connected with an output terminal of the (r+2 M-1 )-th shift register unit, wherein r=1, 2, . . . , N−2 M-1 ,
a plurality of low level signal terminals of the shift register units are connected with a first low level signal line,
a plurality of reset signal terminals of the shift register units are connected with a reset signal line,
forward scan signal terminals of the shift register units are connected with a first scan signal line,
backward scan signal terminals of the shift register units are connected with a second scan signal line, and
the trigger signal terminal of the p-th shift register unit is connected with the output terminal of the (p−1)-th shift register unit through the (p−1)-th gate line.

2. The gate drive circuit of claim 1 , wherein a first signal terminal of the k-th shift register unit is connected with the mod(mod(k−1)/2 M )/2 M )-th clock signal line, and a second signal terminal of the k-th shift register unit is connected with the mod((mod(k−1)/2 M +2 M-1 )/2 M )-th clock signal line, wherein k=1, 2, 3, . . . , N, wherein mod denotes the remainder after division.

3. The gate drive circuit of claim 2 , wherein the clock signal on the i-th clock signal line lags the clock signal on the (i−1)-th clock signal line by more than ½ M clock cycle and less than one clock cycle, wherein i=1, 2, . . . , 2 M −1.

4. The gate drive circuit of claim 1 , wherein during a forward scan, the first scan signal line provides a high level signal and the second scan signal line provides a low level signal.

5. The gate drive circuit of claim 1 , wherein the end signal terminals of the last 2 M-1 shift register units of the gate drive circuit are connected with the first initial trigger signal line.

6. An array substrate, comprising:
a display area; and
a non-display area surrounding the display area, wherein N gate lines are arranged in the display area, and a gate drive circuit is arranged in the non-display area,
wherein the gate drive circuit comprises:
N shift register units, each of which is connected with one of N gate lines of a display panel respectively; and
2 M clock signal lines configured to provide the N shift register units with clock signals, wherein each of the N shift register units is connected with exactly 2 M /2 clock signal lines,
wherein:
N is an even number, and M is a natural number larger than or equal to 2,
a trigger signal terminal of the first shift register unit is connected with a first initial trigger signal line, and a trigger signal terminal of the p-th shift register unit is connected with an output terminal of the (p−1)-th shift register unit, wherein p=2, 3, . . . , N,
an end signal terminal of the r-th shift register unit is connected with an output terminal of the (r+2 M-1 )-th shift register unit, wherein r=1, 2, . . . , N−2 M-1 ,
a plurality of low level signal terminals of the shift register units are connected with a first low level signal line,
a plurality of reset signal terminals of the shift register units are connected with a reset signal line,
forward scan signal terminals of the shift register units are connected with a first scan signal line,
backward scan signal terminals of the shift register units are connected with a second scan signal line, and
the trigger signal terminal of the p-th shift register unit is connected with the output terminal of the (p−1)-th shift register unit through the (p−1)-th gate line.

7. The array substrate of claim 6 , wherein a first signal terminal of the k-th shift register unit is connected with the mod(mod(k−1)/2 M )/2 M )-th clock signal line, and a second signal terminal of the k-th shift register unit is connected with the mod((mod(k−1)/2 M +2 M-1 )/2 M )-th clock signal line, wherein k=1, 2, 3, . . . , N, wherein mod denotes the remainder after division.

8. The array substrate of claim 7 , wherein the clock signal on the i-th clock signal line lags the clock signal on the (i−1)-th clock signal line by more than ½ M clock cycle and less than one clock cycle, wherein i=1, 2, . . . , 2 M −1.

9. The array substrate of claim 6 , wherein during a forward scan, the first scan signal line provides a high level signal and the second scan signal line provides a low level signal.

10. The array substrate of claim 6 , wherein the respective shift register units connected with the odd gate lines are arranged in the non-display area to the left of the display area, and the respective shift register units connected with the even gate lines are arranged in the non-display area to the right of the display area.

11. The array substrate of claim 6 , wherein the respective shift register units connected with the odd gate lines are arranged in the non-display area to the right of the display area, and the respective shift register units connected with the even gate lines are arranged in the non-display area to the left of the display area.

12. A display panel, comprising an array substrate, wherein the array substrate comprises a display area and a non-display area surrounding the display area, wherein N gate lines are arranged in the display area, and a gate drive circuit is arranged in the non-display area,
wherein the gate drive circuit comprises:
N shift register units, each of which is connected with one of N gate lines of a display panel respectively; and
2 M clock signal lines configured to provide the N shift register units with clock signals, wherein each of the N shift register units is connected with exactly 2 M /2 clock signal lines, wherein:
N is an even number, and M is a natural number larger than or equal to 2,
a trigger signal terminal of the first shift register unit is connected with a first initial trigger signal line, and a trigger signal terminal of the p-th shift register unit is connected with an output terminal of the (p−1)-th shift register unit, wherein p=2, 3, . . . , N,
an end signal terminal of the r-th shift register unit is connected with an output terminal of the (r+2 M-1 )-th shift register unit, wherein r=1, 2, . . . , N−2 M-1 ,
a plurality of low level signal terminals of the shift register units are connected with a first low level signal line,
a plurality of reset signal terminals of the shift register units are connected with a reset signal line,
forward scan signal terminals of the shift register units are connected with a first scan signal line,
backward scan signal terminals of the shift register units are connected with a second scan signal line, and
the trigger signal terminal of the p-th shift register unit is connected with the output terminal of the (p−1)-th shift register unit through the (p−1)-th gate line.

13. A display device, comprising a display panel, wherein the display panel comprises an array substrate, wherein the array substrate comprises a display area and a non-display area surrounding the display area, wherein there N gate

Assignees

• Shanghai Tianma Microelectronics Co Ltd
• Tianma Microelectronics Co Ltd

Inventors

• Lou Tenggang

Classifications

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G3/2096 Primary

  Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167) · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2310/0213

  controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power · CPC title