Directed interrupt virtualization

Patent metadata

Field	Value
Publication number	US-11249927-B2
Application number	US-202117234966-A
Country	US
Kind code	B2
Filing date	Apr 20, 2021
Priority date	Feb 14, 2019
Publication date	Feb 15, 2022
Grant date	Feb 15, 2022

Abstract

An interrupt signal is provided to a guest operating system executed using one or more processors of a plurality of processors. One or more bus connected modules are operationally connected with the plurality of processors via a bus and a bus attachment device. The bus attachment device receives an interrupt signal from one of the bus connected modules with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using a mapping table comprised by the bus attachment device and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.

First claim

What is claimed is:

1. A computer program product for providing an interrupt signal to a guest operating system executed using one or more processors of a plurality of processors of a computer system assigned for usage by the guest operating system, the computer program product comprising:
at least one computer readable storage medium readable by at least one processing circuit and storing instructions for performing a method comprising:
receiving, by a bus attachment device of the computer system from a bus connected module of a plurality of bus connected modules operationally coupled to the plurality of processors via the bus attachment device, an interrupt signal with an interrupt target ID, the interrupt target ID identifying one processor of the plurality of processors assigned for usage by the guest operating system as a target processor for handling the interrupt signal;
translating, by the bus attachment device, the interrupt target ID to a logical processor ID of the target processor using a mapping table of the bus attachment device, the mapping table mapping interrupt target IDs of the processors assigned for usage by the guest operating system to logical processor IDs of the plurality of processors; and
forwarding, by the bus attachment device, the interrupt signal to the target processor to handle, the forwarding using the logical processor ID of the target processor to address the target processor directly.

2. The computer program product of claim 1 , wherein the interrupt signal being received is in a form of a message signaled interrupt comprising the interrupt target ID of the target processor.

3. The computer program product of claim 1 , wherein the method further comprises:
retrieving, by the bus attachment device, a copy of a device table entry from a device table stored in a memory operationally coupled with the bus attachment device, the device table entry comprising a direct signaling indicator indicating whether the target processor is to be addressed directly; and
based on the direct signaling indicator indicating a direct forwarding of the interrupt signal, the forwarding of the interrupt signal using the logical processor ID of the target processor to address the target processor directly is executed, else forwarding by the bus attachment device the interrupt signal for handling to the plurality of processors using broadcasting.

4. The computer program product of claim 3 , wherein the method further comprises:
checking, by the bus attachment device, whether the copy of the device table entry is cached in a local cache operationally connected with the bus attachment device;
based on the copy of the device table entry being cached, the retrieving of the copy of the device table entry is a retrieving from the cache; and
based on the copy of the device table entry not being cached, the retrieving of the device table entry is a retrieving from the memory.

5. The computer program product of claim 3 , wherein the memory comprises an interrupt summary vector, the device table entry further comprises an interrupt summary vector address indicator indicating a memory address of the interrupt summary vector, the interrupt summary vector comprising an interrupt summary indicator per bus connected module, each interrupt summary indicator being assigned to a respective bus connected module indicating whether there is an interrupt signal issued by the respective bus connected module to be handled, and wherein the method further comprises:
using, by the bus attachment device, the memory address of the interrupt summary vector to update the interrupt summary indicator assigned to the bus connected module from which the interrupt signal is received such that an updated interrupt summary indicator indicates that there is the interrupt signal issued by the respective bus connected module to be handled.

6. The computer program product of claim 5 , wherein the interrupt summary vector is implemented as a contiguous area.

7. The computer program product of claim 3 , wherein the memory further comprises a directed interrupt summary vector, the device table entry further comprises a directed interrupt summary vector address indicator indicating a memory address of the directed interrupt summary vector, the directed interrupt summary vector comprising a directed interrupt summary indicator per interrupt target ID, each directed interrupt summary indicator being assigned to a respective interrupt target ID indicating whether there is an interrupt signal addressed to the respective interrupt target ID to be handled, and wherein the method further comprises:
using, by the bus attachment device, the memory address of the directed interrupt summary vector to update the directed interrupt summary indicator assigned to the interrupt target ID to which the received interrupt signal is addressed such that an updated directed interrupt summary indicator indicates that there is the interrupt signal addressed to the respective interrupt target ID to be handled.

8. The computer program product of claim 3 , wherein the memory further comprises one or more interrupt signal vectors, the device table entry further comprises an interrupt signal vector address indicator indicating a memory address of an interrupt signal vector of the one or more interrupt signal vectors, each of the interrupt signal vectors comprising one or more interrupt signal indicators, each interrupt signal indicator being assigned to a bus connected module of the one or more bus connected modules and to an interrupt target ID indicating whether an interrupt signal has been received from a respective bus connected module addressed to a respective interrupt target ID, and wherein the method further comprises:
using, by the bus attachment device, the memory address of the interrupt signal vector to select a selected interrupt signal indicator assigned to the bus connected module which issued the interrupt signal and to the interrupt target ID to which the interrupt signal is addressed; and
updating the selected interrupt signal indicator such that the selected interrupt signal indicator indicates that there is the interrupt signal issued by the respective bus connected module and addressed to the respective interrupt target ID to be handled.

9. The computer program product of claim 8 , wherein at least the interrupt signal vector is implemented as a contiguous area.

10. The computer program product of claim 3 , wherein the device table entry further comprises a logical partition ID identifying a logical partition to which the guest operating system is assigned, and wherein the forwarding of the interrupt signal by the bus attachment device further comprises forwarding the logical partition ID with the interrupt signal.

11. The computer program product of claim 1 , wherein the method further comprises retrieving, by the bus attachment device, an interrupt subclass ID identifying an interrupt subclass to which the interrupt signal is assigned, and wherein the forwarding of the interrupt signal by the bus attachment device further comprises forwarding the interrupt subclass ID with the interrupt signal.

12. The computer program product of claim 1 , wherein the method further comprising:
receiving, by the bus attachment device, a request from the bus connected module for a direct memory access for updating status information of the bus connected module in memory, a status update of the bus connected module triggering the interrupt signal; and
based on receiving the request, performing by the bus attachment device the direct memory access to the memory updating the status information of the bus connected module in the memory.

Assignees

• IBM

Inventors

• Raisch Christoph
• Kraemer Marco
• Schmidt Donald William
• Nerz Bernd
• Lehnert Frank Siegfried
• Driever Peter Dana

Classifications

• G06F13/1668

  Details of memory controller · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F9/48

  Program initiating; Program switching, e.g. by interrupt · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title