Direct current measurement of 1/f transistor noise

Patent metadata

Field	Value
Publication number	US-11249130-B2
Application number	US-201715859244-A
Country	US
Kind code	B2
Filing date	Dec 29, 2017
Priority date	Dec 29, 2017
Publication date	Feb 15, 2022
Grant date	Feb 15, 2022

Abstract

A system comprises a noise generator circuit and a noise envelope detector circuit. The noise generator circuit comprises a first amplifier including a single transistor pair that is operable to generate 1/f noise, an output amplifier coupled to the first amplifier and configured to generate a 1/f noise signal as a function of the 1/f noise. The noise envelope detector circuit comprises a low pass filter operable to pass low frequency signals of the 1/f noise signal as a filtered 1/f noise signal, and a second amplifier or a comparator coupled to the low pass filter and operable to output a direct current (DC) voltage signal according to an envelope of the filtered 1/f noise signal, where the DC voltage signal is a function of an envelope of the filtered 1/f noise signal.

First claim

What is claimed is:

1. A method, comprising:
applying, at a noise generator circuit, a first bias current value at a first amplifier to generate a bias current of the first amplifier;
applying, at the noise generator circuit, a second current value to the first amplifier to reduce a voltage offset of the first amplifier;
applying, at the noise generator circuit, at least one drain current to a transistor pair to generate 1/f noise;
filtering, with a noise envelope detector circuit, the 1/f noise to generate filtered 1/f noise; and
comparing, at the noise envelope detector circuit, the filtered 1/f noise with a reference voltage to output a direct current (DC) output voltage.

2. The method of claim 1 , wherein comparing the filtered 1/f noise with the reference voltage comprises comparing the filtered 1/f noise with the reference voltage at a comparator or a second amplifier.

3. The method of claim 1 , further comprising outputting a high DC value as the DC output voltage when the reference voltage is greater than an envelope of the filtered 1/f noise.

4. The method of claim 3 , further comprising outputting a low DC value as the DC output voltage when the reference voltage is lesser than the envelope of the filtered 1/f noise.

5. The method of claim 1 , wherein the first bias current value is an external bias current.

6. The method of claim 1 , wherein the second current value is a DC offset current.

7. The method of claim 1 , wherein the transistor pair is an NMOS transistor pair.

8. The method of claim 1 , wherein the generated 1/f noise is based on a channel current density of the transistor pair.

9. The method of claim 1 , wherein the at least one drain current is a linear factor of the first bias current value.

10. The method of claim 1 , wherein the transistor pair generates greater than 80 percent (%) of the 1/f noise.

11. The method of claim 1 , wherein the filtering step includes applying the 1/f noise to a low-pass filter at an input of the comparator to filter out the high frequency components of the noise signal and to pass signals lower than the cutoff frequency of the low-pass filter.

12. The method of claim 11 , wherein the low-pass filter passes signals lower than 5 kHz.

13. The method of claim 11 , wherein the low-pass filter is implemented as an active resistor R and capacitor C (“active RC”) low-pass filter (LPF) that is operable as a “Miller capacitor” to multiply the effective value of the capacitor through a miller effect in order to move the pass-band of the active RC LPF to a lower frequency.

14. A method of forming an integrated circuit, comprising:
forming a noise generator circuit over a semiconductor substrate, the noise-generator circuit including:
an amplifier configured to generate a bias current in response to a first input current value, and to produce a voltage offset in response to a second input current value; and
a transistor pair configured to generate 1/f noise in response to an applied drain current;
forming a noise envelope detector circuit to generate filtered 1/f noise in response to the 1/f noise, the noise envelope detector circuit configured to generate a direct current (DC) output voltage in response to the filtered 1/f noise.

15. The method of claim 14 , wherein the noise envelope detector circuit is formed over the semiconductor substrate.

16. The method of claim 14 , wherein the noise envelope detector circuit is configured to compare the filtered 1/f noise to a reference voltage.

17. The method of claim 16 , wherein the noise envelope detector circuit is configured to output a high DC value as the DC output voltage when the reference voltage is greater than an envelope of the filtered 1/f noise.

18. The method of claim 16 , further comprising outputting a low DC value as the DC output voltage when the reference voltage is lesser than the envelope of the filtered 1/f noise.

19. The method of claim 14 , wherein the bias current is an external bias current.

20. The method of claim 14 , wherein the transistor pair is an NMOS transistor pair.

Assignees

• Texas Instruments Inc

Inventors

• Wang Yuguo
• Loveless Steven
• Chatterjee Tathagata
• Doorenbos Jerry

Classifications

• G01R31/2626 Primary

  for measuring noise (measuring noise factor in general G01R29/26) · CPC title