Optimized Multi Gain LNA Enabling Low Current and High Linearity Including Highly Linear Active Bypass
US-2020328724-A1 · Oct 15, 2020 · US
US11245372B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11245372-B2 |
| Application number | US-202017005244-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 27, 2020 |
| Priority date | Aug 30, 2019 |
| Publication date | Feb 8, 2022 |
| Grant date | Feb 8, 2022 |
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This disclosure relates to variable-gain amplifiers that include degeneration circuits configured to adapt to a gain mode that is currently being implemented. For example, a variable-gain amplifier can operate in a plurality of gain modes to amplify a signal with different levels of amplification. The variable-gain amplifier can include a gain circuit configured to amplify a signal and a degeneration circuit coupled to the gain circuit. The degeneration circuit can include an inductor and a switching-capacitive arm coupled in parallel to the inductor. The degeneration circuit can operate based on a current gain mode to change an inductance for the variable-gain amplifier.
Opening claim text (preview).
What is claimed is: 1. A variable-gain amplifier comprising: a gain circuit configured to amplify a signal and to operate in a plurality of gain modes; and a degeneration circuit coupled to the gain circuit, the degeneration circuit including an inductor and a switching-capacitive arm coupled in parallel to the inductor, the switching-capacitive arm including a capacitor and a switch coupled in series, wherein the switch is configured to be placed in: an open state when the gain circuit operates in a first gain mode from among the plurality of gain modes; and a closed state when the gain circuit operates in a second gain mode from among the plurality of gain modes, the first gain mode being associated with more gain than the second gain mode. 2. The variable-gain amplifier of claim 1 wherein the switch includes at least one of a transistor or a mechanical switch. 3. The variable-gain amplifier of claim 1 wherein the switching-capacitive arm is a first switching-capacitive arm and the degeneration circuit further includes a second switching-capacitive arm coupled in parallel to the inductor. 4. The variable-gain amplifier of claim 1 wherein the gain circuit includes a transistor having a gate or base coupled to an input node and a drain or collector coupled to an output node, and the degeneration circuit is coupled to a source or emitter of the transistor. 5. The variable-gain amplifier of claim 1 wherein the variable-gain amplifier is implemented within a low noise amplifier. 6. The variable-gain amplifier of claim 1 wherein the gain circuit includes a transistor, and wherein the inductor, the switching-capacitive arm, and a source or emitter of the transistor are coupled to a common node. 7. A variable-gain amplifier comprising: a transistor including a gate or base coupled to an input node and a drain or collector coupled to an output node; and a degeneration circuit coupled to a source or emitter of the transistor, the degeneration circuit including an inductor and a switching-capacitive arm coupled in parallel to the inductor, the switching-capacitive arm including a capacitor and a switch coupled in series, wherein the switch is configured to be placed in: an open state when the variable-gain amplifier implements a first gain mode; and a closed state when the variable-gain amplifier implements a second gain mode, the first gain mode being associated with more gain than the second gain mode. 8. The variable-gain amplifier of claim 7 wherein the switch includes one or more of a transistor or a mechanical switch. 9. The variable-gain amplifier of claim 7 wherein the switching-capacitive arm is a first switching-capacitive arm and the degeneration circuit further includes a second switching-capacitive arm coupled in parallel to the inductor. 10. The variable-gain amplifier of claim 7 wherein the variable-gain amplifier is implemented within a low noise amplifier. 11. The variable-gain amplifier of claim 7 wherein the inductor, the switching-capacitive arm, and the source or emitter of the transistor are coupled to a common node. 12. A radio-frequency module comprising: a low noise amplifier configured to amplify a first signal; a power amplifier configured to amplify a second signal; and a controller coupled to at least one of the low noise amplifier or the power amplifier, wherein at least one of the low noise amplifier or the power amplifier includes a transistor and a degeneration circuit coupled to the transistor, the transistor including a gate or base coupled to an input node and a drain or collector coupled to an output node, the degeneration circuit including an inductor and a switching-capacitive arm coupled in parallel to the inductor, the switching-capacitive arm including a capacitor and a switch coupled in series, and wherein the controller is configured to: control the switch to implement an open state for a first gain mode; and control the switch to implement a closed state for a second gain mode, the first gain mode being associated with more gain than the second gain mode. 13. The radio-frequency module of claim 9 wherein the switch includes at least one of a transistor or a mechanical switch. 14. The radio-frequency module of claim 12 wherein the switching-capacitive arm is a first switching-capacitive arm and the degeneration circuit further includes a second switching-capacitive arm coupled in parallel to the inductor. 15. A radio-frequency device comprising: the radio frequency module of claim 12 ; and an antenna configured to receive the first signal and transmit the second signal. 16. The radio-frequency module of claim 12 wherein the inductor, the switching-capacitive arm, and a source or emitter of the transistor are coupled to a common node.
being an amplifying element · CPC title
Transmit/receive switching · CPC title
in integrated circuits · CPC title
with semiconductor devices only · CPC title
the amplifier being a radio frequency amplifier · CPC title
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