Stacked high barrier III-V power semiconductor diode

Patent metadata

Field	Value
Publication number	US-11245012-B2
Application number	US-202016863585-A
Country	US
Kind code	B2
Filing date	Apr 30, 2020
Priority date	Apr 30, 2019
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

A stacked high barrier III-V power semiconductor diode having an at least regionally formed first metallic terminal contact layer and a heavily doped semiconductor contact region of a first conductivity type with a first lattice constant, a drift layer of a second conductivity type, a heavily doped metamorphic buffer layer sequence of the second conductivity type is formed. The metamorphic buffer layer sequence has an upper side with the first lattice constant and a lower side with a second lattice constant. The first lattice constant is greater than the second lattice constant. The upper side of the metamorphic buffer layer sequence is arranged in the direction of the drift layer. A second metallic terminal contact layer is arranged below the lower side of the metamorphic buffer layer sequence. The second metallic terminal contact layer is integrally bonded with a semiconductor contact layer.

First claim

What is claimed is:

1. A stacked high barrier III-V power semiconductor diode comprising:
an at least regionally formed first metallic terminal contact layer;
a first heavily doped semiconductor contact region of a first conductivity type with a dopant concentration greater than 1×10 18 N/cm 3 and with a first lattice constant;
a doped intermediate layer of a first conductivity type with a dopant concentration of less than 5×10 15 N/cm 3 , with the first lattice constant and with a thickness between 1 micron and 30 microns;
a drift layer of a second conductivity type with the first lattice constant and with a layer thickness greater than 10 microns;
a heavily doped metamorphic buffer layer sequence of the second conductivity type with a layer thickness of more than 0.2 microns and less than 20 microns, wherein the metamorphic buffer layer sequence has an upper side with the first lattice constant and a lower side with a second lattice constant, the upper side being arranged in a direction of the drift layer; and
a second metallic terminal contact layer formed below the lower side of the metamorphic buffer layer sequence,
wherein the first lattice constant is greater than the second lattice constant,
wherein the first metallic terminal contact layer, the first heavily doped semiconductor contact region, the intermediate layer, the drift layer, the metamorphic buffer layer sequence, and the second metallic terminal contact layer are ordered in the order mentioned,
wherein the second metallic terminal contact layer is integrally bonded with a semiconductor contact layer, and
wherein at least the first heavily doped semiconductor contact region and the drift layer and the metamorphic buffer layer sequence comprise a III-V compound or consist of a III-V compound.

2. The stacked high barrier III-V power semiconductor diode according to claim 1 , wherein the first heavily doped metamorphic buffer layer sequence is of the second conductivity type or the first conductivity type and has a dopant concentration greater than 5×10 17 N/cm 3 or greater than 1×10 17 N/cm 3 or greater than 3×10 16 N/cm 3 or greater than 1×10 16 N/cm 3 .

3. The stacked high barrier III-V power semiconductor diode according to claim 1 , wherein the first metallic terminal contact layer is integrally bonded with the semiconductor contact region and the second metallic terminal contact layer is integrally bonded with the semiconductor contact layer.

4. The stacked high barrier III-V power semiconductor diode according to claim 1 , wherein a substrate layer of the first conductivity type or the second conductivity type is provided below the metamorphic buffer layer sequence and the substrate layer comprises the second lattice constant and Ge or GaAs or InP or consists of Ge or GaAs or InP.

5. The stacked high barrier III-V power semiconductor diode according to claim 1 , wherein a substrate layer of the first conductivity type or the second conductivity type is provided below the metamorphic buffer layer sequence and the substrate layer comprises the second lattice constant and a layer sequence made of InP and GaAs or consists of the layer sequence made of InP and GaAs.

6. The stacked high barrier III-V power semiconductor diode according to claim 1 , wherein a second heavily doped semiconductor layer is the semiconductor contact layer with the second lattice constant is arranged between the metamorphic buffer layer sequence and the second metallic terminal contact layer, and the second heavily doped semiconductor layer is of the second conductivity type or the first conductivity type and has a dopant concentration greater than 1×10 18 N/cm 3 and a layer thickness above 0.1 microns.

7. The stacked high barrier III-V power semiconductor diode according to claim 1 , wherein a substrate layer of the first conductivity type or the second conductivity type is provided below the metamorphic buffer layer sequence, wherein a second heavily doped semiconductor layer formed below the metamorphic buffer layer sequence is part of the substrate layer, and wherein the substrate layer is formed as the semiconductor contact layer of the second conductivity type or the first conductivity type and has a thickness between 10 microns and 450 microns or between 350 microns and 1000 microns.

8. The stacked high barrier III-V power semiconductor diode according to claim 1 , wherein a second heavily doped semiconductor layer with the first lattice constant is formed and the second heavily doped semiconductor layer is of the second conductivity type or the first conductivity type and has a dopant concentration greater than 1×10 18 N/cm 3 and a layer thickness of more than 0.1 microns.

9. The stacked high barrier III-V power semiconductor diode according to claim 1 , wherein the semiconductor contact region and the semiconductor layers arranged between the semiconductor contact region and the upper side of the metamorphic buffer layer sequence each comprise an InGaAs compound or consist of InGaAs.

10. The stacked high barrier III-V power semiconductor diode according to claim 1 , wherein the first conductivity type is p and the second conductivity type is n or the first conductivity type is n and the second conductivity type is p.

11. The stacked high barrier III-V power semiconductor diode according to claim 1 , wherein the semiconductor contact region is formed as a planar layer or is trough-shaped.

12. The stacked high barrier III-V power semiconductor diode according to claim 6 , wherein the another doped semiconductor layer consists of GaAs or comprises a GaAs compound and the drift layer and the semiconductor contact region each comprise an InGaAs compound or consist of InGaAs.

13. The stacked high barrier III-V power semiconductor diode according to claim 6 , wherein the second heavily doped semiconductor layer and the drift layer and the semiconductor contact region each comprise an InGaAs compound or consist of InGaAs.

14. The stacked high barrier III-V power semiconductor diode according to claim 1 , wherein the semiconductor contact region and the semiconductor layers are formed monolithically.

15. The stacked high barrier III-V power semiconductor diode according to claim 1 , wherein the drift layer consists of In x Ga 1-x As with 0.1<x<0.6.

16. The stacked high barrier III-V power semiconductor diode according to claim 1 , wherein the metamorphic buffer layer sequence consists of In x Ga 1-x As with wherein on a lower side adjacent to the substrate layer, x=0 or x is between 0 and 0.02, x increases from the lower side to the upper side up to a limit value of x=0.6 or x=0.4 and wherein the increase of x between the individual layers of the buffer layer sequence from the lower side to the upper side of the buffer layer sequence is formed to be stepwise or linear or otherwise increasing.

17. The stacked high barrier III-V power semiconductor diode according to claim 1 , wherein the drift layer is directly adjacent to the first heavily doped semiconductor contact region.

18. The stacked high barrier III-V power semiconductor diode according to claim 1 , wherein the heavily doped metamorphic buffer layer sequence has dopant concentration greater than 5×10 17 N/cm 3 .

Assignees

• Azur Space Solar Power Gmbh

Inventors

• Fuhrmann Daniel
• Keller Gregor
• WAECHTER Clemens

Classifications

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

• H10D62/106

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title

• H10D8/00 Primary

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

• H10D8/411

  PN diodes having planar bodies · CPC title

• H10D62/82

  Heterojunctions · CPC title