Electronic device using group III nitride semiconductor having specified dislocation density, oxygen/electron concentration, and active layer thickness

Patent metadata

Field	Value
Publication number	US-9305772-B2
Application number	US-201414460097-A
Country	US
Kind code	B2
Filing date	Aug 14, 2014
Priority date	Apr 7, 2006
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

The present invention discloses an electronic device using a group III nitride substrate fabricated via the ammonothermal method. By utilizing the high-electron concentration of ammonothermally grown substrates having the dislocation density less than 10 5 cm −2 , combined with a high-purity active layer of Ga 1-x-y Al x In y N (0≦x≦1, 0≦y≦1) grown by a vapor phase method, the device can attain high level of breakdown voltage as well as low on-resistance. To realize a good matching between the ammonothermally grown substrate and the high-purity active layer, a transition layer is optionally introduced. The active layer is thicker than a depletion region created by a device structure in the active layer.

First claim

What is claimed is:

1. An electronic device comprising a substrate of Ga 1-x1-y1 Al x1 In y1 N (0≦x1≦1, 0≦y1≦1), an active layer of Ga 1-x2-y2 Al x2 In y2 N (0≦x2≦1, 0≦y2≦1) on a first side of the substrate, a back ohmic contact on a second side opposite to the first side of the substrate, and a depletion region having a depth in the active layer, wherein;
(a) the substrate has a dislocation density of less than 10 5 cm −2 ;
(b) the substrate has an electron concentration or an oxygen concentration greater than 10 18 cm −3 ;
(c) the active layer has an electron concentration or an oxygen concentration less than 10 18 cm −3 ; and
(d) the depletion region does not extend into the substrate for any applied voltage within an operation range of the device, and the depletion region has a Schottky contact or a metal-insulator-semiconductor structure associated with the depletion region;
(e) a current blocking layer between the substrate and the active layer, wherein the current blocking layer has an opening for an electrical current;
(f) a front ohmic contact adjacent to the Schottky contact or the metal-insulator-semiconductor structure;
and wherein the front ohmic contact and the Schottky contact or the metal-insulator-semiconductor structure are positioned to regulate an electric current through the front ohmic contact to the back ohmic contact with a voltage applied across the front ohmic contact and the Schottky contact or the metal-insulator-semiconductor structure.

2. An electronic device according to claim 1 wherein the electron concentration of the active layer is less than 10 16 cm −3 .

3. An electronic device according to claim 1 wherein the oxygen concentration of the active layer is less than 10 16 cm −3 .

4. An electronic device according to claim 1 and further comprising a transition layer between the substrate and the active layer wherein said transition layer is deposited by vapor phase epitaxy and comprises Ga 1-x3-y3 Al x3 In y3 N (0≦x3≦1, 0≦y3≦1).

5. An electronic device according to claim 4 wherein the oxygen concentration of the active layer is less than 10 16 cm −3 .

6. An electronic device according to claim 4 wherein the electron concentration of the active layer is less than 10 16 cm −3 .

7. An electronic device according to claim 4 wherein the depletion region extends into the transition layer.

8. An electronic device according to claim 4 wherein the transition layer has an impurity concentration or alloy composition that varies along a growth direction so that lattice matching is realized at an interface between the substrate and the transition layer and at an interface between the transition layer and the active layer.

9. An electronic device according to claim 4 wherein the transition layer is sufficiently thick to bury cracks created at an interface between the substrate and the transition layer.

10. An electronic device according to claim 4 wherein the transition layer is doped with an impurity which prevents diffusion of impurities contained in the substrate.

11. An electronic device according to claim 1 wherein the substrate is made of a wafer fabricated from a bulk crystal of Ga 1-x1-y1 Al x1 In y1 N (0≦x1≦1, 0≦y1≦1) grown in supercritical ammonia.

12. An electronic device according to claim 1 wherein the substrate contains sodium at a concentration of greater than about 10 16 cm −3 and the active layer has a sodium concentration at least 100 times less than the sodium concentration of the substrate.

13. An electronic device according to claim 1 wherein the active layer is grown by vapor phase epitaxy.

14. An electronic device according to claim 1 wherein the substrate is a c plane wafer with miscut more than 0.1 degree and less than 5 degrees.

15. An electronic device according to claim 1 wherein the current blocking layer comprises silicon dioxide.

16. An electronic device according to claim 1 wherein the current blocking layer comprises a gas.

17. An electronic device according to claim 16 wherein the gas is air.

18. An electronic device according to claim 1 wherein the current blocking layer comprises p-type or semi-insulating Ga 1-x-y Al x In y N (0≦x≦1, 0≦y≦1).

19. An electronic device according to claim 1 further comprising a region of high electron concentration underneath the front ohmic contact.

20. An electronic device according to claim 1 wherein the depletion region has a p-n junction associated with the depletion region and further comprising an additional n-type semiconductor on the p-n junction to form a bipolar transistor.

21. An electronic device according to claim 1 wherein x1=x2=0 and y1=y2=0.

Assignees

• Sixpoint Materials Inc
• Seoul Semiconductor Co Ltd

Inventors

• Hashimoto Tadao

Classifications

• H10P14/3822

  Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing · CPC title

• H10P14/3448

  Delta-doping · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10P14/2925

  Surface structures · CPC title

• H10P14/2921

  being crystalline insulating materials · CPC title