Thin film transistor, manufacturing method thereof, sensor

Patent metadata

Field	Value
Publication number	US-11245008-B2
Application number	US-201916642522-A
Country	US
Kind code	B2
Filing date	Jul 24, 2019
Priority date	Aug 3, 2018
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

The present application provides a TFT, a manufacturing method thereof, and a sensor. The TFT includes a substrate, and a source, a drain and an active layer on the substrate. The active layer includes a microchannel, and the thin film transistor is configured to detect a sample in the microchannel. When a sample to be detected enters the microchannel, the electron distribution in the active layer would be affected, which causes fluctuations in the TFT characteristics. By detecting such fluctuations, detecting the composition and property of the liquid to be detected may be achieved. Moreover, by virtue of the microchannel, the sample may be precisely controlled. The impact of the external environment may be reduced and the detection accuracy can be enhanced. Continuous monitoring instead of one-time detection of the sample may be achieved and the sample detection efficiency may be improved.

First claim

The invention claimed is:

1. A thin film transistor, comprising:
a substrate, and
a source, a drain and an active layer on the substrate,
wherein the active layer comprises a first portion and a second portion on the source and the drain respectively, and
wherein the first portion and the second portion are at least partially spaced apart to form a microchannel between the first portion and the second portion,
wherein the first portion and the second portion of the active layer extend over the source and the drain respectively in a vertical direction facing away from a main surface of the substrate, so that the first portion covers the source and the second portion covers the drain,
wherein an area of a cross section of each of the first portion and the second portion parallel to the main surface of the substrate increases in the vertical direction so that a top of the first portion and a top of the second portion are connected to each other, such that the microchannel comprises a top-closed channel structure,
wherein the thin film transistor further comprises a gate, and
wherein the gate is between the substrate and the active layer in the vertical direction.

2. The thin film transistor according to claim 1 ,
wherein an orthographic projection of the first portion on the substrate overlaps an orthographic projection of the source on the substrate, and
wherein an orthographic projection of the second portion on the substrate overlaps an orthographic projection of the drain on the substrate.

3. The thin film transistor according to claim 1 ,
wherein a spacing between the source and the drain is greater than or equal to 5 nanometers and less than or equal to 50 micrometers, and
wherein the source and the drain both have a height greater than or equal to 5 nanometers and less than or equal to 50 micrometers.

4. A sensor comprising the thin film transistor according to claim 1 .

5. The sensor according to claim 4 ,
wherein an area of a cross section of each of the first portion and the second portion parallel to the main surface of the substrate increases in the vertical direction so that a top of the first portion and a top of the second portion are connected to each other, such that the microchannel comprises a top-closed channel structure,
wherein the thin film transistor further comprises a gate, the gate is between the substrate and the active layer in the vertical direction.

6. The sensor according to claim 4 ,
wherein an orthographic projection of the first portion on the substrate overlaps an orthographic projection of the source on the substrate, and
wherein an orthographic projection of the second portion on the substrate overlaps an orthographic projection of the drain on the substrate.

7. The sensor according to claim 4 ,
wherein a spacing between the source and the drain is greater than or equal to 5 nanometers and less than or equal to 50 micrometers, and
wherein the source and the drain both have a height greater than or equal to 5 nanometers and less than or equal to 50 micrometers.

8. The sensor according to claim 4 ,
wherein the thin film transistor further comprises a gate and a gate insulating layer,
wherein the gate, the gate insulating layer, the source, the drain and the active layer are stacked on the substrate successively, and
wherein at least a portion of the gate insulating layer serves as a bottom of the microchannel.

9. The sensor according to claim 8 ,
wherein the active layer further comprises a third portion between the source and the drain, and
wherein the third portion is in direct contact with the gate insulating layer and serves as the bottom of the microchannel.

10. A thin film transistor, comprising:
a substrate, and
a source, a drain and an active layer on the substrate,
wherein the active layer comprises a first portion and a second portion on the source and the drain respectively, and
wherein the first portion and the second portion are at least partially spaced apart to form a microchannel between the first portion and the second portion,
wherein the first portion and the second portion of the active layer extend over the source and the drain respectively in a vertical direction facing away from a main surface of the substrate, so that the first portion covers the source and the second portion covers the drain, wherein the thin film transistor further comprises:
a gate and a gate insulating layer,
wherein the gate, the gate insulating layer, the source, the drain and the active layer are stacked on the substrate successively, and
wherein at least a portion of an upper surface of the gate insulating layer facing away the substrate serves as a bottom of the microchannel.

11. The thin film transistor according to claim 10 ,
wherein the active layer further comprises a third portion between the source and the drain, and
wherein the third portion is in direct contact with the gate insulating layer and serves as the bottom of the microchannel.

12. A method for manufacturing a thin film transistor, comprising:
providing a substrate;
forming a source and a drain on the substrate; and
forming an active layer on the substrate on which the source and the drain are formed,
wherein the active layer comprises a first portion and a second portion on the source and the drain respectively, and
wherein the first portion and the second portion are at least partially spaced apart to form a microchannel between the first portion and the second portion,
wherein the first portion and the second portion of the active layer extend over the source and the drain respectively in a vertical direction facing away from a main surface of the substrate, so that the first portion covers the source and the second portion covers the drain,
wherein an area of a cross section of each of the first portion and the second portion parallel to the main surface of the substrate increases in the vertical direction so that a top of the first portion and a top of the second portion are connected to each other, such that the microchannel comprises a top-closed channel structure,
wherein the thin film transistor further comprises a gate, and
wherein the gate is between the substrate and the active layer in the vertical direction.

13. The method according to claim 12 , wherein the forming the active layer comprises:
by taking the source and the drain as growing points, forming the first portion and the second portion of the active layer on the substrate respectively by a sputtering process.

14. The method according to claim 12 , further comprising:
forming a gate and a gate insulating layer on the substrate prior to forming the source and the drain,
wherein the forming the active layer further comprises forming a third portion of the active layer on the gate insulating layer with a material of the active layer, and
wherein the third portion serves as a bottom of the microchannel.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Ma Xiaochen
• Yuan Guangcai
• Ning ce
• Hu hehe
• Gu Xin

Classifications

• H10D30/0312

  characterised by the gate electrodes · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• H10D30/673

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title