Array substrate and method for manufacturing the same, and display device

Patent metadata

Field	Value
Publication number	US-9373649-B2
Application number	US-201414422342-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Sep 26, 2013
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

The invention belongs to the field of display technology, and particularly provides an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a base substrate, and a thin film transistor and driving electrodes provided on the base substrate, the thin film transistor includes a gate, a gate insulating layer, an active layer, a source and a drain, the driving electrodes include a slit-shaped electrode and a plate-shaped electrode which are located in different layers and at least partially overlap with each other in the orthographic projection direction, the source, the drain and the active layer are formed so that part of their bottom surfaces are located in the same plane, and a resin layer is further provided between the thin film transistor and the plate-shaped electrode.

First claim

The invention claimed is:

1. An array substrate, including a base substrate, and a thin film transistor and driving electrodes provided on the base substrate, the thin film transistor including a gate, a gate insulating layer, an active layer, a source and a drain, and the driving electrodes including a slit-shaped electrode and a plate-shaped electrode which are provided in different layers and at least partially overlap with each other in the orthographic projection direction, wherein the source, the drain and the active layer are formed so that part of their bottom surfaces are located in the same lane and a resin layer is provided between the thin film transistor and the plate-shaped electrode;
wherein the gate is provided on the base substrate, the gate insulating layer is provided on the gate, the source and the drain are provided on the gate insulating layer with an interval therebetween, the source and the drain partially overlap with the gate in the orthographic projection direction, respectively, and the active layer is provided within a spacer region formed between the source and the drain, and extends to a top surface of the source and a top surface of a part of the drain so that bottom surfaces of the source, the drain and a art of the active layer are all located on a top surface of the gate insulating layer;
wherein a first protection layer is provided on the active layer, and the first protection layer and the active layer completely overlap with each other in the orthographic projection direction.

2. The array substrate of claim 1 , wherein the resin layer is provided on the first protection layer, the plate-shaped electrode is provided on the resin layer, the thickness of a region, which is provided with the plate-shaped electrode, of the resin layer is larger than that of other regions, a second protection layer is provided on the plate-shaped electrode, and the slit-shaped electrode is provided on the second protection layer.

3. The array substrate of claim 2 , wherein the thickness of the region, which is provided with the plate-shaped electrode, of the resin layer is larger than that of other regions by 50-100 nm.

4. The array substrate of claim 1 , wherein the plate-shaped electrode is a common electrode, and the slit-shaped electrode is a pixel electrode; or the plate-shaped electrode is a pixel electrode, and the slit-shaped electrode is a common electrode.

5. The array substrate of claim 4 , further including a common electrode line provided in the same layer as the gate, wherein a first via hole is provided in a region of the resin layer corresponding to the drain, a second via hole is provided in a region of the resin layer corresponding to the common electrode line, a third via hole is provided in a region of the second protection layer corresponding to the drain, and a fourth via hole is provided in a region of the gate insulating layer corresponding to the common electrode line, and the pixel electrode is electrically connected to the drain through the first via hole and the third via hole, and the common electrode is electrically connected to the common electrode line through the second via hole and the fourth via hole.

6. The array substrate of claim 1 , wherein the resin layer is made of organic resin, the organic resin includes acrylic film-forming resin, phenolic resin-typed film-forming resin, vinyl polymer film-forming resin or polymide film-forming resin, and the resin layer has a thickness in a range of 900-2100 nm.

7. The array substrate of claim 1 , wherein the active layer is made of a metal oxide semiconductor material which includes indium gallium zinc oxide, indium oxide, zinc oxide or indium tin zinc oxide, and the active layer has a thickness of 20-60 nm.

8. The array substrate of claim 1 , wherein the active layer is made of a metal oxide semiconductor material which includes indium gallium zinc oxide, indium oxide, zinc oxide or indium tin zinc oxide, and the active layer has a thickness of 20-60 nm.

9. The array substrate of claim 2 , wherein the first protection layer and the second protection layer are mono-layered or multi-layered composite laminated structures formed of silicon oxide, silicon nitride, hafnium oxide or aluminum oxide, the first protection layer has a thickness in a range of 90-210 nm, and the second protection layer has a thickness in a range of 190-310 nm.

10. A display device, including the array substrate of claim 1 .

11. A method for manufacturing an array substrate, the array substrate including a base substrate, and a thin film transistor and driving electrodes provided on the base substrate, the thin film transistor including a gate, a gate insulating layer, an active layer, a source and a drain, and the driving electrodes including a slit-shaped electrode and a plate-shaped electrode which are provided in different layers and at least partially overlap with each other in the orthographic projection direction, wherein the source, the drain and the active layer are formed so that part of their bottom surfaces are located in the same plane, and a resin layer is provided between the thin film transistor and the plate-shaped electrode, the method includes:
forming patterns of the source, the drain and the active layer by two patterning processes so that part of bottom surfaces of the source, the drain and the active layer are located in the same plane; and
forming a pattern including the resin layer and the plate-shaped electrode by one patterning process.

12. The method of claim 11 , before the step of forming patterns of the source, the drain and the active layer by two patterning processes so that part of bottom surfaces of the source, the drain and the active layer are located in the same plane, further including:
forming a pattern including the gate on the base substrate by one patterning process.

13. The method of claim 12 , wherein the step of forming patterns of the source, the drain and the active layer by two patterning processes so that part of bottom surfaces of the source, the drain and the active layer are located in the same plane includes:
forming a gate insulating layer on the base substrate formed with the pattern including the gate, and forming a pattern including the source and the drain on the gate insulating layer so that the source and the drain are provided with an interval therebetween; and
on the base substrate subjected to the above step, forming a pattern including the active layer and a first protection layer by one patterning process so that the active layer is provided within a spacer region formed between the source and the drain, and extends to a top surface of the source and a top surface of a part of the drain, bottom surfaces of the source, the drain and a part of the active layer are all located on a top surface of the gate insulating layer, and the first protection layer and the active layer completely overlap with each other in the orthographic projection direction.

14. The method of claim 11 , wherein by the step of forming a pattern including the resin layer and the plate-shaped electrode by one patterning process, the thickness of a region, which is provided with the plate-shaped electrode, of the resin layer is made to be larger than that of other regions.

15. The method of claim 14 , wherein by the step of forming a pattern including the resin layer and the plate-shaped electrode by one patterning process, the thickness of the region, which is provided with the plate-shaped electrode, of the resin layer is made to be larger than that of other regions by 50-100 nm.

16. The method of claim 11 ,

Assignees

• Boe Technology Group Co Ltd

Inventors

• Ning ce
• Yang Wei
• Wang Ke

Classifications

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D86/451 Primary

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title