Thin film transistor array substrate and organic light emitting diode panel

US11244994B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11244994-B2
Application numberUS-201916650873-A
CountryUS
Kind codeB2
Filing dateDec 25, 2019
Priority dateOct 23, 2019
Publication dateFeb 8, 2022
Grant dateFeb 8, 2022

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A thin film transistor (TFT) array substrate and an organic light emitting diode (OLED) panel are provided. The TFT array substrate includes a display area and a non-display area. The non-display area is provided with a plurality of gate traces connected to a control chip, the TFT array substrate includes: a flexible substrate includes a metal jumper-joint sublayer disposed in the non-display area, wherein the metal jumper-joint sublayer is adjacent to the display area; and a thin film transistor is disposed on the flexible substrate, wherein the thin film transistor layer includes a plurality of thin film transistors correspondingly disposed in the display area, and a gate trace of each of the thin film transistors and the gate trace of the non-display area are connected by a jumper joint arrangement through the metal jumper-joint sublayer.

First claim

Opening claim text (preview).

What is claimed is: 1. An organic light emitting diode (OLED) panel, comprising: a thin film transistor (TFT) array substrate comprising a display area and a non-display area, wherein the non-display area is provided with a plurality of gate traces connected to a control chip, the TFT array substrate includes a flexible substrate and a thin film transistor layer, the flexible substrate includes a metal jumper-joint sublayer disposed in the non-display area, the metal jumper-joint sublayer is adjacent to the display area, the thin film transistor layer is disposed on the flexible substrate, and the thin film transistor layer includes a plurality of thin film transistors correspondingly disposed in the display area, a gate trace of each of the thin film transistors and a gate trace of the non-display area are connected by a jumper joint arrangement through the metal jumper-joint sublayer, the flexible substrate includes a first flexible sublayer, an inorganic sublayer, the metal jumper-joint sublayer, and a second flexible sublayer stacked in sequence; a planarization layer is disposed on the thin film transistor layer; a pixel definition layer is disposed on the planarization layer; an organic electroluminescent device layer is disposed on the pixel definition layer and located in the display area; and an encapsulation layer is disposed on the organic electroluminescent device layer. 2. The OLED panel according to claim 1 , wherein the metal jumper-joint sublayer comprises a first titanium metal sublayer, an aluminum metal sublayer, and a second titanium metal sublayer stacked in sequence. 3. The OLED panel according to claim 1 , wherein the metal jumper-joint sublayer is correspondingly disposed in a bending area of the non-display area. 4. The OLED panel according to claim 1 , wherein the second flexible sublayer is provided with a first through hole and a second through hole, the first through hole is used for connecting the gate trace of the thin film transistor to the metal jumper-joint sublayer, and the second through hole is used for connecting the gate trace of the non-display area to the metal jumper-joint sublayer. 5. The OLED panel according to claim 1 , wherein the thin film transistor layer comprises a TFT active area, a gate insulation sublayer, the gate traces, an interlayer dielectric sublayer, and a plurality of source/drain traces stacked in sequence, the gate insulation sublayer is provided with a third through hole at a position corresponding to the metal jumper-joint sublayer, and the third through hole is used for connecting the gate trace of the thin film transistor to the metal jumper-joint sublayer. 6. The OLED panel according to claim 1 , wherein the TFT array substrate further comprises a buffer layer disposed between the flexible substrate and the thin film transistor layer, the buffer layer is provided with a fourth through hole at a position corresponding to the metal jumper-joint sublayer, and the fourth through hole is used for connecting the gate trace of the thin film transistor to the metal jumper-joint sublayer. 7. The OLED panel according to claim 1 , wherein the encapsulation layer comprises a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. 8. A thin film transistor (TFT) array substrate, comprising a display area and a non-display area, wherein the non-display area is provided with a plurality of gate traces connected to a control chip, the TFT array substrate includes: a flexible substrate includes a metal jumper-joint sublayer disposed in the non-display area, the metal jumper-joint sublayer adjacent to the display area; and a thin film transistor layer is disposed on the flexible substrate, and the thin film transistor layer includes a plurality of thin film transistors correspondingly disposed in the display area, a gate trace of each of the thin film transistors and a gate trace of the non-display area are connected by a jumper joint arrangement through the metal jumper-joint sublayer. 9. The TFT array substrate according to claim 8 , wherein the flexible substrate comprises a first flexible sublayer, an inorganic sublayer, the metal jumper-joint sublayer, and a second flexible sublayer stacked in sequence. 10. The TFT array substrate according to claim 9 , wherein the metal jumper-joint sublayer comprises a first titanium metal sublayer, an aluminum metal sublayer, and a second titanium metal sublayer stacked in sequence. 11. The TFT array substrate according to claim 9 , wherein the metal jumper-joint sublayer is correspondingly disposed in a bending area of the non-display area. 12. The TFT array substrate according to claim 9 , wherein the second flexible sublayer is provided with a first through hole and a second through hole, the first through hole is used for connecting the gate trace of the thin film transistor to the metal jumper-joint sublayer, and the second through hole is used for connecting the gate trace of the non-display area to the metal jumper-joint sublayer. 13. The TFT array substrate according to claim 8 , wherein the thin film transistor layer comprises a TFT active area, a gate insulation sublayer, the gate traces, an interlayer dielectric sublayer, and a plurality of source/drain traces stacked in sequence, the gate insulation sublayer is provided with a third through hole at a position corresponding to the metal jumper-joint sublayer, and the third through hole is used for connecting the gate trace of the thin film transistor to the metal jumper-joint sublayer. 14. The TFT array substrate according to claim 13 , wherein the TFT array substrate further comprises a buffer layer disposed between the flexible substrate and the thin film transistor layer, the buffer layer is provided with a fourth through hole at a position corresponding to the metal jumper-joint sublayer, and the fourth through hole is used for connecting the gate trace of the thin film transistor to the metal jumper-joint sublayer. 15. An organic light emitting diode (OLED) panel, comprising: a thin film transistor (TFT) array substrate comprising a display area and a non-display area, wherein the non-display area is provided with a plurality of gate traces connected to a control chip, the TFT array substrate includes a flexible substrate and a thin film transistor layer, the flexible substrate includes a metal jumper-joint sublayer disposed in the non-display area, the metal jumper-joint sublayer is adjacent to the display area, the thin film transistor layer is disposed on the flexible substrate, and the thin film transistor layer includes a plurality of thin film transistors correspondingly disposed in the display area, a gate trace of each of the thin film transistors and a gate trace of the non-display area are connected by a jumper joint arrangement through the metal jumper-joint sublayer; an organic electroluminescent device layer is disposed on the thin film transistor layer and located in the display area; and an encapsulation layer is disposed on the organic electroluminescent device layer. 16. The OLED panel according to claim 15 , wherein the flexible substrate comprises a first flexible sublayer, an inorganic sublayer, the metal jumper-joint sublayer, and a second flexible sublayer stacked in sequence. 17. The OLED panel according to claim 16 , wherein the metal jumper-joint sublayer is correspondingly disposed in a bending area of the non-display area.

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11244994B2 cover?
A thin film transistor (TFT) array substrate and an organic light emitting diode (OLED) panel are provided. The TFT array substrate includes a display area and a non-display area. The non-display area is provided with a plurality of gate traces connected to a control chip, the TFT array substrate includes: a flexible substrate includes a metal jumper-joint sublayer disposed in the non-display a…
Who is the assignee on this patent?
Wuhan China Star Optoelectronics Semiconductor Display Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K59/131. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 08 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).