Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11239373-B2
Application number	US-202016942775-A
Country	US
Kind code	B2
Filing date	Jul 30, 2020
Priority date	Jun 18, 2020
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

A semiconductor device includes a dielectric structure, a first source/drain electrode, a second source/drain electrode, an oxide semiconductor layer, a gate dielectric layer, and a first gate electrode. The first source/drain electrode is disposed in the dielectric structure. The oxide semiconductor layer is disposed on the first source/drain electrode in a vertical direction. The second source/drain electrode disposed on the oxide semiconductor layer in the vertical direction. The gate dielectric layer is disposed on the dielectric structure and surrounds the oxide semiconductor layer in a horizontal direction. The gate dielectric layer includes a first portion and a second portion. The first portion is elongated in the horizontal direction. The second portion is disposed on the first portion and elongated in the vertical direction. The first gate electrode is disposed on the first portion of the gate dielectric layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a dielectric structure;
a first source/drain electrode disposed in the dielectric structure;
an oxide semiconductor layer disposed on the first source/drain electrode in a vertical direction;
a second source/drain electrode disposed on the oxide semiconductor layer in the vertical direction;
a gate dielectric layer disposed on the dielectric structure and surrounding the oxide semiconductor layer in a horizontal direction, wherein the gate dielectric layer comprises:
a first portion elongated in the horizontal direction; and
a second portion disposed on the first portion and elongated in the vertical direction; and

a first gate electrode disposed on the first portion of the gate dielectric layer.

2. The semiconductor device according to claim 1 , wherein a part of the second portion of the gate dielectric layer is disposed between the first gate electrode and the oxide semiconductor layer in the horizontal direction, and a part of the first portion of the gate dielectric layer is disposed between the first gate electrode and the dielectric structure in the vertical direction.

3. The semiconductor device according to claim 1 , wherein a top surface of the second portion of the gate dielectric layer is higher than a top surface of the first portion of the gate dielectric layer in the vertical direction.

4. The semiconductor device according to claim 1 , wherein the first gate electrode is disposed on a top surface of the first portion of the gate dielectric layer, and a top surface of the first gate electrode is lower than a top surface of the second portion of the gate dielectric layer in the vertical direction.

5. The semiconductor device according to claim 1 , wherein the first gate electrode is disposed on a top surface of the first portion of the gate dielectric layer, and a top surface of the first gate electrode and a top surface of the second portion of the gate dielectric layer are coplanar.

6. The semiconductor device according to claim 1 , further comprising:
a second gate electrode disposed on the first portion of the gate dielectric layer, wherein the first gate electrode and the second gate electrode are disposed at two opposite sides of the oxide semiconductor layer respectively, and the second gate electrode is separated from the first gate electrode.

7. The semiconductor device according to claim 6 , wherein a part of the second portion of the gate dielectric layer is disposed between the first gate electrode and the oxide semiconductor layer in the horizontal direction, and another part of the second portion of the gate dielectric layer is disposed between the second gate electrode and the oxide semiconductor layer in the horizontal direction.

8. The semiconductor device according to claim 6 , wherein a part of the first portion of the gate dielectric layer is disposed between the first gate electrode and the dielectric structure in the vertical direction, and another part of the first portion of the gate dielectric layer is disposed between the second gate electrode and the dielectric structure in the vertical direction.

9. The semiconductor device according to claim 1 , further comprising:
a dielectric layer disposed on the dielectric structure and the first source/drain electrode, wherein the dielectric layer is disposed between the dielectric structure and the gate dielectric layer in the vertical direction, and the oxide semiconductor layer penetrates through the dielectric layer in the vertical direction.

10. The semiconductor device according to claim 1 , further comprising:
a semiconductor substrate, wherein the dielectric structure is disposed on the semiconductor substrate; and
an interconnection structure, wherein at least a part of the interconnection structure is disposed in the dielectric structure, and the first source/drain electrode is electrically connected with the interconnection structure.

11. The semiconductor device according to claim 10 , wherein the interconnection structure penetrates through the first portion of the gate dielectric layer in the vertical direction.

12. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises:
a first layer; and
a second layer disposed on the first layer, wherein a part of the first layer is disposed between the second layer and the first source/drain electrode in the vertical direction, and another part of the first layer is disposed between the second layer and the gate dielectric layer in the horizontal direction.

13. The semiconductor device according to claim 12 , wherein a material composition of the first layer is different from a material composition of the second layer.

14. The semiconductor device according to claim 12 , wherein the first layer comprises a U-shaped structure in a cross-sectional view of the oxide semiconductor layer.

15. The semiconductor device according to claim 1 , wherein the first gate electrode surrounds the oxide semiconductor layer and the gate dielectric layer in the horizontal direction.

16. A manufacturing method of a semiconductor device, comprising:
forming a first source/drain electrode in a dielectric structure;
forming an oxide semiconductor layer on the first source/drain electrode in a vertical direction;
forming a gate dielectric layer on the dielectric structure, wherein the gate dielectric layer surrounds the oxide semiconductor layer in a horizontal direction, and the gate dielectric layer comprises:
a first portion elongated in the horizontal direction; and
a second portion disposed on the first portion and elongated in the vertical direction;

forming a first gate electrode on the first portion of the gate dielectric layer; and
forming a second source/drain electrode on the oxide semiconductor layer in the vertical direction.

17. The manufacturing method of the semiconductor device according to claim 16 , wherein a method of forming the oxide semiconductor layer comprises:
forming a first dielectric layer on the dielectric structure and the first source/drain electrode;
forming a second dielectric layer on the first dielectric layer;
forming an opening penetrating through the first dielectric layer and the second dielectric layer in the vertical direction and exposing a part of the first source/drain electrode; and
forming the oxide semiconductor layer in the opening.

18. The manufacturing method of the semiconductor device according to claim 17 , wherein the method of forming the oxide semiconductor layer further comprises:
removing at least a part of the second dielectric layer before the step of forming the gate dielectric layer for exposing a sidewall of the oxide semiconductor layer, wherein the second portion of the gate dielectric layer is formed on the sidewall of the oxide semiconductor layer.

19. The manufacturing method of the semiconductor device according to claim 16 , further comprising:
forming a second gate electrode on the first portion of the gate dielectric layer, wherein the first gate electrode and the second gate electrode are disposed at two opposite sides of the oxide semiconductor layer respectively, and the second gate electrode is separated from the first gate electrode.

20. The manufacturing method of the semiconductor device according to claim 19 , wherein the first gate electrode and the second gate electrode are formed concurrently by performing a patterning process to a gate material layer formed on the gate dielectric layer.

Assignees

• United Microelectronics Corp

Inventors

• Li Xiang
• Chen Ding-Lung

Classifications

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10D30/6728

  Vertical TFTs · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title