Semiconductor device

Patent metadata

Field	Value
Publication number	US-11239357-B2
Application number	US-202016780965-A
Country	US
Kind code	B2
Filing date	Feb 4, 2020
Priority date	Aug 23, 2019
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a metal-including portion being conductive, an insulating portion, a gate electrode, a second electrode, a first interconnect layer, and a second interconnect layer. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region and the metal-including portion are provided on portions of the second semiconductor region. The insulating portion is arranged in a second direction with the third semiconductor region, the second semiconductor region, and a portion of the first semiconductor region. The gate electrode and the second electrode are provided inside the insulating portion. The first interconnect layer is electrically connected to the gate electrode. The second interconnect layer is electrically connected to the metal-including portion and the second electrode.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first electrode;
a first semiconductor region provided on the first electrode and electrically connected to the first electrode, the first semiconductor region being of a first conductivity type;
a second semiconductor region provided on the first semiconductor region, the second semiconductor region being of a second conductivity type;
a third semiconductor region provided on a portion of the second semiconductor region, the third semiconductor region being of the first conductivity type;
a metal-including portion provided on an other portion of the second semiconductor region, the metal-including portion being electrically conductive;
an insulating portion arranged in a second direction with the third semiconductor region, the second semiconductor region, and a portion of the first semiconductor region, the second direction being perpendicular to a first direction from the first electrode toward the first semiconductor region;
a gate electrode provided inside the insulating portion, the gate electrode opposing the second semiconductor region in the second direction with a gate insulating layer interposed;
a second electrode provided inside the insulating portion and electrically isolated from the gate electrode, the second electrode including a portion opposing the first semiconductor region in the second direction;
a first interconnect layer electrically connected to the gate electrode and provided, with a first insulating layer interposed, on the gate electrode and a portion of the metal-including portion; and
a second interconnect layer provided to be separated from the first interconnect layer and electrically connected to the metal-including portion and the second electrode.

2. The device according to claim 1 , wherein
pluralities are provided in the second direction for the insulating portion, the gate electrode, and the second electrode, and
the first interconnect layer is electrically connected to the plurality of gate electrodes and provided on the plurality of gate electrodes with the first insulating layer interposed.

3. The device according to claim 1 , wherein the second interconnect layer is provided on the first interconnect layer with a second insulating layer interposed.

4. The device according to claim 3 , further comprising:
a first connector connecting the first interconnect layer and the gate electrode and being provided between the gate electrode and the first interconnect layer in the first direction; and
a second connector connecting the second interconnect layer and the second electrode and being provided between the second electrode and the second interconnect layer in the first direction.

5. The device according to claim 3 , further comprising a third interconnect layer provided, with the first insulating layer interposed, on the second electrode and an other portion of the metal-including portion,
the third interconnect layer being arranged with the first interconnect layer in a third direction,
the third direction being perpendicular to the first direction and crossing the second direction,
the third interconnect layer being electrically connected to the second electrode, the metal-including portion, and the second interconnect layer.

6. The device according to claim 1 , wherein
pluralities are provided in a third direction for the insulating portion, the gate electrode, the second electrode, and the first interconnect layer, the third direction being perpendicular to the first direction and crossing the second direction, and
each of the plurality of first interconnect layers is provided on the plurality of gate electrodes and electrically connected to the plurality of gate electrodes.

7. The device according to claim 6 , further comprising a third connector connecting the metal-including portion and the second interconnect layer,
the third connector being provided between the first interconnect layers in the third direction.

8. The device according to claim 6 , wherein one of the first interconnect layers is provided on two of the gate electrodes next to each other in the third direction.

9. The device according to claim 6 , wherein a distance between the first interconnect layers next to each other in the third direction is longer than a distance between the second electrodes next to each other in the third direction.

10. The device according to claim 6 , wherein
the plurality of gate electrodes includes a first gate electrode, and a second gate electrode next to the first gate electrode in the third direction, and
a position in the second direction of the first gate electrode is different from a position in the second direction of the second gate electrode.

11. The device according to claim 1 , wherein an upper surface of the portion of the metal-including portion is positioned higher than an upper surface of the third semiconductor region.

12. The device according to claim 1 , wherein
the second semiconductor region, the third semiconductor region, the metal-including portion, the insulating portion, the gate electrode, and the second electrode extend in a third direction, the third direction being perpendicular to the first direction and crossing the second direction,
a third interconnect layer is provided on a portion of each of the second semiconductor region, the third semiconductor region, the metal-including portion, the insulating portion, the gate electrode, and the second electrode, and
the second interconnect layer is provided on an other portion of each of the second semiconductor region, the third semiconductor region, the metal-including portion, the insulating portion, the gate electrode, and the second electrode.

13. The device according to claim 1 , wherein the metal-including portion includes at least one selected from the group consisting of aluminum, tungsten, copper, titanium, cobalt, and nickel.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Nishiwaki Tatsuya
• Katou Hiroaki
• Kobayashi Kenya
• Kachi Tsuyoshi

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title

• H10D62/127 Primary

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title