Semiconductor die for determining load of through silicon via and semiconductor device including the same

Patent metadata

Field	Value
Publication number	US-11239210-B2
Application number	US-202017124762-A
Country	US
Kind code	B2
Filing date	Dec 17, 2020
Priority date	Mar 12, 2018
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first semiconductor die including,
first delay stages connected in series, the first delay stages configured to receive a test signal, one of the first delay stages configured to output a first delay signal,
second delay stages connected in series, the second delay stages configured to receive the test signal, one of the second delay stages configured to output a second delay signal,
at least one first through silicon via connected to at least one output terminal of output terminals of the first delay stages, and
processing circuitry configured to determine a load of the at least one first through silicon via and at least one second through silicon via based on the first delay signal and the second delay signal; and

a second semiconductor die stacked on the first semiconductor die, the second semiconductor die including the at least one second through silicon via electrically connected to the at least one first through silicon via.

2. The semiconductor device of claim 1 , wherein
a first propagation delay of one of the first delay stages connected to the at least one of the output terminals is influenced by the at least one first through silicon via, and
output terminals of the second delay stages are not connected to the at least one first through silicon via and the at least one second through silicon via such that a second propagation delay of each of the second delay stages is not influenced by the at least one first through silicon via and the at least one second through silicon via.

3. The semiconductor device of claim 1 , wherein
each of the second delay stages includes a same at least one logic gate as corresponding ones of the first delay stages, and
each of the second delay stages is adjacent to each of the first delay stages.

4. The semiconductor device of claim 1 , wherein the first semiconductor die is a logic die configured to,
receive a command of the second semiconductor die,
transmit the command to the second semiconductor die, and
receive a processing result of the command from the second semiconductor die.

5. The semiconductor device of claim 1 , further comprising:
at least one bump electrically connecting the at least one first through silicon via and the at least one second through silicon via, wherein
the processing circuitry is configured to determine a load of the at least one first through silicon via, the at least one second through silicon via, and the at least one bump.

6. A semiconductor device, comprising:
a first semiconductor die including at least one first through silicon via; and
a second semiconductor die stacked on the first semiconductor die, the second semiconductor die including,
first delay stages connected in series, the first delay stages including output terminals, one of the first delay stages configured to output a first delay signal,
second delay stages connected in series, one of the second delay stages configured to output a second delay signal,
at least one second through silicon via electrically connected to at least one of the output terminals of the first delay stages and the at least one first through silicon via,
a transmitter configured to transmit a test signal received from the first semiconductor die to the first delay stages and the second delay stages, and
processing circuitry configured to determine a load of the at least one first through silicon via and the at least one second through silicon via based on the first delay signal and the second delay signal.

7. The semiconductor device of claim 6 , further comprising:
a third semiconductor die stacked on the second semiconductor die, the third semiconductor die including at least one third through silicon via electrically connected to the at least one first through silicon via and the at least one second through silicon via, wherein
the processing circuitry is configured to determine the load of the at least one first through silicon via, the at least one second through silicon via, and the at least one third through silicon via, which are electrically connected to each other.

8. The semiconductor device of claim 6 , wherein a structure of the first semiconductor die is same as structure of the second semiconductor die.

9. The semiconductor device of claim 6 , wherein the first semiconductor die is a logic die configured to,
receive a command of the second semiconductor die,
transmit the command to the second semiconductor die, and
receive a processing result of the command from the second semiconductor die.

10. The semiconductor device of claim 9 , wherein the processing circuitry is further configured to transmit a determination result and a stack identifier of the second semiconductor die to the first semiconductor die.

11. The semiconductor device of claim 10 , wherein the first semiconductor die further comprises:
at least one fourth through silicon via configured to receive the determination result.

12. The semiconductor device of claim 11 , wherein the first semiconductor die further comprises:
at least one fifth through silicon via through which the test signal is transmitted.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Woo Seunghan
• Ryu Je Min
• Oh Reum
• Oh Moonhee
• Lee Bumsuk

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/284

  characterised by structural arrangements for measuring or testing · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title