System and method for a storage controller having a persistent memory interface to local memory

Patent metadata

Field	Value
Publication number	US-11237959-B2
Application number	US-201916711294-A
Country	US
Kind code	B2
Filing date	Dec 11, 2019
Priority date	Jun 12, 2017
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

First claim

What is claimed is:

1. A method, comprising:
receiving, via a host interface of a primary controller, a plurality of write operations from a host;
updating, via a logical-to-physical address manager of a secondary controller, a logical-to-physical address table in a persistent memory based on the plurality of write operations;
collecting, via the secondary controller, a group of changes to the logical-to-physical address table in the persistent memory based on the updating;
sending, via a controller interface of the secondary controller in communication with the primary controller, at least a sub-set of the group of changes for storage in a non-volatile memory; and
when at least a portion of the logical-to-physical address table in the persistent memory is valid, declining to copy the at least a portion of the logical-to-physical address table from the non-volatile memory into the persistent memory,
wherein a data storage system comprises the second controller, the persistent memory and the non-volatile memory, and
wherein the data storage system is separate and different from the host.

2. The method of claim 1 , wherein sending the at least the sub-set of the group of changes comprises most-recent changes for each logical address of the updating.

3. The method of claim 1 , wherein sending the at least the sub-set of the group of changes excludes duplicate and stale changes to the logical-to-physical address table.

4. The method of claim 1 , wherein the storage in the non-volatile memory is separate from the persistent memory.

5. The method of claim 1 , further comprising:
increasing, via the secondary controller, a queue depth of commands sent to the persistent memory to match a bandwidth between the primary controller and a volatile memory.

6. The method of claim 1 , wherein the non-volatile memory comprises a three-dimensional memory.

7. The method of claim 1 , further comprising:
disconnecting the host interface from the host; and
reconnecting the host interface to the host.

8. The method of claim 1 , further comprising:
in response to detecting power loss, causing the at least a portion of the logical-to-physical address table to remain in or to be written to the persistent memory for power off storage; and
in response to the host re-booting after the power loss, verifying whether the at least a portion of the logical-to-physical address table in the persistent memory is valid.

9. The method of claim 1 , wherein:
the data storage system comprises the primary controller; and
the primary controller is different from the secondary controller.

10. A data storage device, comprising:
volatile memory;
a non-volatile memory;
a first controller for communication with the non-volatile memory via a memory interface, wherein the first controller comprises a host interface configured to receive a plurality of write operations from a host; and
a second controller for communication with the first controller via a controller interface of the first controller and the volatile memory, wherein the second controller comprises a remote logical-to-physical address manager configured to access and update, based on the plurality of write operations, a logical-to-physical address table copied from the non-volatile memory to the volatile memory,
wherein the second controller is further configured to collect, based on the updating, a group of changes to the logical-to-physical address table in the volatile memory and send, via the controller interface, at least a sub-set of the group of changes for storage in the non-volatile memory,
wherein when at least a portion of the logical-to-physical address table in the volatile memory is valid, the data storage device is configured to cause declining to copy the at least a portion of the logical-to-physical address table from the non-volatile memory into the volatile memory, and
wherein the data storage device is separate and different from the host.

11. The data storage device of claim 10 , wherein the second controller is configured to include most-recent changes for each logical address of the updating of the logical-to-physical address table within the at least the sub-set of the group of changes.

12. The data storage device of claim 10 , wherein the second controller is configured to exclude duplicate and stale changes to the logical-to-physical address table from the at least the sub-set of the group of changes.

13. The data storage device of claim 10 , wherein the non-volatile memory comprises a three-dimensional memory.

14. The data storage device of claim 10 , wherein the data storage device is removably connected to the host.

15. A data storage device comprising:
means for receiving a plurality of write operations from a host;
means for updating a logical-to-physical address table in a persistent memory based on the plurality of write operations;
means for collecting a group of changes to the logical-to-physical address table in the persistent memory based on the updating of the logical-to-physical address table; and
means for sending at least a sub-set of the group of changes for storage in a non-volatile memory,
means for declining to copy at least a portion of the logical-to-physical address table from the non-volatile memory into the persistent memory, when the at least a portion of the logical-to-physical address table in the persistent memory is valid,
wherein the data storage device comprises the persistent memory and the non-volatile memory, and
wherein the data storage device is separate and different from the host.

16. The data storage device of claim 15 , wherein the means for receiving comprises a host interface of a primary controller.

17. The data storage device of claim 15 , wherein the means for updating comprises a logical-to-physical address manager of a secondary controller.

18. The data storage device of claim 15 , wherein the means for sending comprises a controller interface of a secondary controller in communication with the means for receiving.

19. The data storage device of claim 15 , wherein the persistent memory and the non-volatile memory are separate.

20. The data storage device of claim 15 , wherein the means for sending is configured to exclude duplicate and stale changes to the logical-to-physical address table from the at least the sub-set of the group of changes.

Assignees

• Western Digital Tech Inc

Inventors

• Helmick Daniel
• Lucky Richard S
• Gold Stephen
• Jones Ryan R

Classifications

• H10B99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• G06F2212/7208

  Multiple device management, e.g. distributing data over multiple flash devices · CPC title

• G06F12/0623 Primary

  for memory modules · CPC title

• G06F12/1072

  Decentralised address translation, e.g. in distributed shared memory systems · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title