Memory device and operating method of same

Patent metadata

Field	Value
Publication number	US-2016299710-A1
Application number	US-201514683630-A
Country	US
Kind code	A1
Filing date	Apr 10, 2015
Priority date	Apr 10, 2015
Publication date	Oct 13, 2016
Grant date	—

Abstract

A memory device includes a memory controller and a non-volatile memory communicatively coupled to the memory controller and storing a mapping table and a journal table. The memory controller is configured to write data and a logical address of the data into the non-volatile memory, load mapping information related to the logical address of the data from the mapping table of the non-volatile memory into a mapping cache of the memory controller, update the mapping cache with an updated mapping relationship between the logical address of the data and a physical address of the data, and perform a journaling operation to write the updated mapping relationship into the journal table.

First claim

What is claimed is:

1 . A memory device, comprising:
a memory controller; and a non-volatile memory communicatively coupled to the memory controller and storing a mapping table and a journal table, wherein the memory controller is configured to:
write data and a logical address of the data into the non-volatile memory;
load mapping information related to the logical address of the data from the mapping table of the non-volatile memory into a mapping cache of the memory controller;
update the mapping cache with an updated mapping relationship between the logical address of the data and a physical address of the data; and
perform a journaling operation to write the updated mapping relationship into the journal table.

2 . The memory device of claim 1 , wherein,
the non-volatile memory further includes a plurality of data blocks, the memory controller being further configured to:
write the data and the logical address into one of the plurality of data blocks, and
perform the journaling operation when the one of the plurality of data blocks is full.

3 . The memory device of claim 2 , wherein the memory controller is further configured to assign a free data block for writing future data when the one of the plurality of data blocks is full.

4 . The memory device of claim 1 , wherein the memory controller is further configured to record operations performed on the mapping cache between two consecutive journaling operations in a write back cache.

5 . The memory device of claim 4 , wherein the memory controller is configured to perform the journaling operation by writing the information stored in the write back cache into the journal table.

6 . The memory device of claim 1 , wherein the memory controller is further configured to recover the mapping information in the mapping cache based on information stored in the journal table after power has been restored following a power interruption.

7 . The memory device of claim 1 , wherein the non-volatile memory is a flash memory.

8 . The memory device of claim 1 , wherein the memory controller includes a volatile memory.

9 . A method for controlling a memory device by a memory controller, the memory device including a non-volatile memory which stores a mapping table and a journal table,
the method comprising:
writing data and a logical address of the data into the non-volatile memory;
loading mapping information related to the logical address of the data from the mapping table of the non-volatile memory into a mapping cache of the memory controller;
updating the mapping cache with an updated mapping relationship between the logical address of the data and a physical address of the data; and
performing a journaling operation to write the updated mapping relationship into the journal table.

10 . The method of claim 9 , wherein,
the non-volatile memory further includes a plurality of data blocks, the writing into the non-volatile memory includes writing the data and the logical address into one of the plurality of data blocks, and the journaling operation is performed when the one of the plurality of data blocks is full.

11 . The method of claim 10 , further including assigning a free data block for writing future data when the one of the plurality of data blocks is full.

12 . The method of claim 9 , wherein the method further includes recording operations performed on the mapping cache between two consecutive journaling operations in a write back cache.

13 . The method of claim 12 , wherein the journaling operation includes writing the information stored in the write back cache into the journal table.

14 . The method of claim 9 , further comprising:
recovering the mapping information in the mapping cache based on information stored in the journal table after power has been restored following a power interruption.

15 . A memory controller for controlling a non-volatile memory, the non-volatile memory stores a mapping table and a journal table,
the memory controller comprising processing circuitry configured to:
write data and a logical address of the data into the non-volatile memory;
load mapping information related to the logical address of the data from the mapping table of the non-volatile memory into a mapping cache of the memory controller;
update the mapping cache with an updated mapping relationship between the logical address of the data and a physical address of the data; and
perform a journaling operation to write the updated mapping relationship into the journal table.

16 . The memory controller of claim 15 , wherein,
the non-volatile memory further includes a plurality of data blocks, the processing circuitry of the memory controller being configured to:
write the data and the logical address into one of the plurality of data blocks, and
perform the journaling operation when the one of the plurality of data blocks is full.

17 . The memory controller of claim 16 , wherein the processing circuitry of the memory controller is configured to assign a free data block for writing future data when the one of the plurality of data blocks is full.

18 . The memory controller of claim 15 , wherein the processing circuitry of the memory controller is further configured to record operations performed on the mapping cache between two consecutive journaling operations in a write back cache.

19 . The memory controller of claim 18 , wherein the processing circuitry of the memory controller is configured to perform the journaling operation by writing the information stored in the write back cache into the journal table.

20 . The memory controller of claim 15 , wherein the processing circuitry of the memory controller is further configured to recover the mapping information in the mapping cache based on information stored in the journal table after power has been restored following a power interruption.

Assignees

• Macronix Int Co Ltd

Inventors

• Chang Yu-Ming
• Huang Wei-Chieh
• Huang Li-Chun
• Chang Hung-Sheng
• Li Hsiang-Pang
• Liu Ting-Yu
• Liu Chien-Hsin
• Kuo Nai-Ping

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F11/1441

  Resetting or repowering · CPC title

• G06F11/141

  for bus or memory accesses · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title