Method for accessing extended memory, device, and system

Patent metadata

Field	Value
Publication number	US-11237728-B2
Application number	US-202016744795-A
Country	US
Kind code	B2
Filing date	Jan 16, 2020
Priority date	Apr 23, 2015
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

In a method for accessing an extended memory, after receiving a first memory access request from a processor system in a computer, an extended memory controller sends a read request for obtaining to-be-accessed data to the extended memory and return, to the processor system, a first response message indicating the to-be-accessed data has not been obtained. The extended memory controller writes the to-be-accessed data into a data buffer after receiving the to-be-accessed data returned by the extended memory. After receiving, from the processor system, a second memory access request comprising a second access address, the extended memory controller returns, to the processor system, the to-be-accessed data in the data buffer in response to the second memory access request, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data.

First claim

What is claimed is:

1. A method performed by an extended memory controller for accessing an extended memory of a computer, the method comprising:
receiving, from a processor system of the computer, a first memory access request for reading data stored in the extended memory, wherein the first memory access request comprises a first access address of the data;
sending, to the processor system, in response to the first memory access request, and before obtaining the data from the extended memory, a first response message indicating that the extended memory controller has not obtained the data;
receiving, from the processor system, after receiving the first memory access request, and after obtaining the data from the extended memory, a second memory access request comprising a second access address that is different from the first access address;
making a determination that the first access address and the second access address correspond to a same physical address of the data; and
sending the data to the processor system in response to the second memory access request and the determination.

2. The method of claim 1 , further comprising:
receiving, from the processor system before obtaining the data from the extended memory, a third memory access request comprising a third access address, wherein the third access address is different from the first access address and the second access address, and wherein the third access address corresponds to the physical address; and
sending, to the processor system in response to the third memory access request, a third response message indicating that the extended memory controller has not obtained the data.

3. The method of claim 1 , wherein the first access address comprises a first bank address and a first row address, wherein the second access address comprises the first bank address and a second row address, and wherein the first row address is different from the second row address.

4. The method of claim 1 , further comprising creating a record in a data buffer, wherein the record comprises a tag field and a validity field, wherein the tag field corresponds to the physical address, and wherein, before receiving the data from the extended memory, the validity field indicates invalidity.

5. The method of claim 4 , further comprising:
receiving the data from the extended memory;
storing, in response to receiving the data, the data in a data field of the record; and
setting, in response to storing the data, the validity field of the record to indicate validity.

6. An extended memory system comprising:
an extended memory; and
an extended memory controller coupled to the extended memory and configured to:
receive, from a processor system of a computer, a first memory access request for reading data stored in the extended memory, wherein the first memory access request comprises a first access address of the data;
send, to the processor system, in response to the first memory access request, and before obtaining the data from the extended memory, a first response message indicating that the extended memory controller has not obtained the data;
receive, from the processor system, after receiving the first memory access request, and after obtaining the data from the extended memory, a second memory access request comprising a second access address that is different from the first access address;
make a determination that the first access address and the second access address correspond to a same physical address of the data; and
send the data to the processor system in response to the second memory access request and the determination.

7. The extended memory system of claim 6 , wherein the extended memory controller is further configured to:
receive, from the processor system before obtaining the data from the extended memory, a third memory access request comprising a third access address, wherein the third access address is different from the first access address and the second access address, and wherein the third access address corresponds to the physical address of the data; and
send, to the processor system in response to the third memory access request, a third response message indicating that the extended memory controller has not obtained the data.

8. The extended memory system of claim 6 , wherein the first access address comprises a first bank address and a first row address, wherein the second access address comprises the first bank address and a second row address, and wherein the first row address is different from the second row address.

9. The extended memory system of claim 6 , wherein the extended memory controller is further configured to create a record in a data buffer, wherein the record comprises a tag field and a validity field, wherein the tag field corresponds to the physical address, and wherein, before the extended memory controller receives the data from the extended memory, the validity field indicates invalidity.

10. The extended memory system of claim 9 , wherein the extended memory controller is further configured to:
receive the data from the extended memory;
store, in response to receiving the data, the data in a data field of the record; and
set, in response to storing the data, the validity field of the record to indicate validity.

11. A computer system comprising:
an extended memory system comprising:
an extended memory controller, and
an extended memory configured to store data; and

a processor system coupled to the extended memory system and configured to:
generate, according to a storage address of the data, N+1 memory access requests, wherein each of the N+1 memory access requests comprises a different access address corresponding to a same physical address of the data in the extended memory; and
send the N+1 memory access requests to the extended memory controller for accessing the data from the extended memory.

12. The computer system of claim 11 , wherein the extended memory controller is configured to:
receive, from the processor system, a first memory access request of the N+1 memory access requests, wherein the first memory access request is for reading the data and comprises a first access address of the data;
send, to the processor system, in response to the first memory access request, and before obtaining the data from the extended memory, a first response message indicating that the extended memory controller has not obtained the data;
receive, from the processor system, after receiving the first memory access request, and after obtaining the data from the extended memory, a second memory access request of the N+1 memory access requests, wherein the second memory access request comprises a second access address that is different from the first access address;
make a determination that the first access address and the second access address correspond to a physical address of the data; and
send the data to the processor system in response to the second memory access request and the determination.

13. The computer system of claim 12 , wherein the extended memory controller is further configured to:
receive, from the processor system before obtaining the data from the extended memory, a third memory access request of the N+1 memory access requests, wherein the third memory access request comprises a third access address, wherein the third access address is different from the first access address and the second access address, and wherein the third access address corresponds to the physical address of the data; and
send, to the processor system in response to the third memory access request, a third response message indicating that

Assignees

• Huawei Tech Co Ltd

Inventors

• Cui Zehan
• Chen Mingyu
• Liu Yao
• Ruan Yuan

Classifications

• G06F12/0215 Primary

  with look ahead addressing means · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/06

  Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers} · CPC title

• G06F12/0623

  for memory modules · CPC title