Display panel and manufacture method thereof, and display apparatus

US11237437B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11237437-B2
Application numberUS-201816080119-A
CountryUS
Kind codeB2
Filing dateJan 15, 2018
Priority dateJun 27, 2017
Publication dateFeb 1, 2022
Grant dateFeb 1, 2022

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A display panel and a manufacture method thereof, and a display apparatus are provided. The display panel includes a first substrate and a second substrate which arranged opposite to each other. The first substrate includes a display region and a peripheral region, a conduction section is in the peripheral region of the first substrate, and the conduction section is electrically connected with a grounded section. The second substrate includes a display region and a peripheral region, a black matrix is at least in the peripheral region of the second substrate, and the black matrix is electrically connected with the conduction section.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel, comprising: a first substrate and a second substrate, arranged opposite to each other, wherein the first substrate comprises a display region and a peripheral region, a conduction section is in the peripheral region of the first substrate, and the conduction section is electrically connected with a grounded section; and the second substrate comprises a display region and a peripheral region, wherein a black matrix is at least in the peripheral region of the second substrate, and the black matrix is electrically connected with the conduction section, wherein the conduction section comprises at least one first conductive layer, and the at least one first conductive layer is respectively in a same layer as a conductive layer in the display region of the first substrate, wherein the conductive layer in the display region of the first substrate comprises a light shielding layer, and the first conductive layer is in a same layer as the light shielding layer. 2. The display panel according to claim 1 , wherein a thickness of the first conductive layer in the peripheral region of the first substrate is greater than a thickness of a conductive layer, which is in a same layer as the first conductive layer, in the display region of the first substrate, and the first conductive layer is electrically connected with the black matrix. 3. The display panel according to claim 1 , wherein the black matrix is further in the display region of the second substrate, and a thickness of the black matrix in the peripheral region of the second substrate is greater than a thickness of the black matrix in the display region of the second substrate. 4. The display panel according to claim 3 , wherein the conduction section is around the peripheral region of the first substrate and forms an enclosed shape, a portion of the black matrix in the peripheral region of the second substrate forms another enclosed shape, and the conduction section is in contact with the black matrix. 5. The display panel according to claim 4 , wherein the second substrate further comprises a planarization layer in the display region of the second substrate, the planarization layer covers the black matrix in the display region of the second substrate, and the thickness of the black matrix in the peripheral region of the second substrate is equal to a sum of the thickness of the black matrix in the display region of the second substrate and a thickness of the planarization layer. 6. The display panel according to claim 1 , further comprising a sealant, wherein the sealant is on a side of the conduction section facing the display region of the first substrate. 7. The display panel according to claim 1 , further comprising a conductive adhesive, wherein the conduction section is electrically connected with the grounded section via the conductive adhesive. 8. The display panel according to claim 1 , wherein the display panel is a fully embedded capacitive touch screen. 9. A display apparatus, comprising the display panel according to claim 1 . 10. The display apparatus according to claim 9 , further comprising a metal frame, wherein the grounded section comprises the metal frame. 11. A manufacture method of a display panel, comprising: providing a first substrate; and providing a second substrate and positioning the second substrate opposite to the first substrate, wherein the first substrate comprises a display region and a peripheral region, a conduction section is in the peripheral region of the first substrate, and the conduction section is electrically connected with a grounded section; and the second substrate comprises a display region and a peripheral region, wherein a black matrix is at least in the peripheral area of the second substrate, and the black matrix is electrically connected with the conduction section, wherein the conduction section comprises at least one first conductive layer, and the at least one first conductive layer is respectively in a same layer as a conductive layer in the display region of the first substrate, wherein the conductive layer in the display region of the first substrate comprises a light shielding layer, and the first conductive layer is in a same layer as the light shielding layer. 12. A display panel, comprising: a first substrate and a second substrate, arranged opposite to each other, wherein the first substrate comprises a display region and a peripheral region, a conduction section is in the peripheral region of the first substrate, and the conduction section is electrically connected with a grounded section; and the second substrate comprises a display region and a peripheral region, wherein a black matrix is at least in the peripheral region of the second substrate, and the black matrix is electrically connected with the conduction section, wherein the conduction section comprises at least one first conductive layer, and the at least one first conductive layer is respectively in a same layer as a conductive layer in the display region of the first substrate, a thin film transistor is in the display region of the first substrate, the thin film transistor comprises a gate electrode and a source/drain electrode, and the first conductive layer is in a same layer as a metal layer where the source/drain electrode is located. 13. The display panel according to claim 12 , wherein the conduction section further comprises an insulating layer and a second conductive layer, the insulating layer covers the first conductive layer, the second conductive layer is electrically connected with the first conductive layer through at least one via hole in the insulating layer, and the second conductive layer is electrically connected with the black matrix. 14. The display panel according to claim 13 , wherein the first substrate further comprises a pixel electrode, and the second conductive layer is in a same layer as the pixel electrode; or the first substrate further comprises a common electrode, and the second conductive layer is in a same layer as the common electrode. 15. The display panel according to claim 12 , wherein the black matrix is further in the display region of the second substrate, and a thickness of the black matrix in the peripheral region of the second substrate is greater than a thickness of the black matrix in the display region of the second substrate. 16. The display panel according to claim 15 , wherein the conduction section is around the peripheral region of the first substrate and forms an enclosed shape, a portion of the black matrix in the peripheral region of the second substrate forms another enclosed shape, and the conduction section is in contact with the black matrix. 17. The display panel according to claim 16 , wherein the second substrate further comprises a planarization layer in the display region of the second substrate, the planarization layer covers the black matrix in the display region of the second substrate, and the thickness of the black matrix in the peripheral region of the second substrate is equal to a sum of the thickness of the black matrix in the display region of the second substrate and a thickness of the planarization layer. 18. The display panel according to claim 12 , further comprising a sealant, wherein the sealant is on a side of the conduction section facing the display region of the first substrate. 19. The display panel according to claim 12 , further comprising a conductive adhesive, wherein the conduction section is electrically

Assignees

Inventors

Classifications

  • characterised by the substrates · CPC title

  • characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

  • for connecting multiple chips together · CPC title

  • Interconnections, e.g. wiring lines or terminals · CPC title

  • comprising light absorbing layers, e.g. black layers · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11237437B2 cover?
A display panel and a manufacture method thereof, and a display apparatus are provided. The display panel includes a first substrate and a second substrate which arranged opposite to each other. The first substrate includes a display region and a peripheral region, a conduction section is in the peripheral region of the first substrate, and the conduction section is electrically connected with …
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Ordos Yuansheng Optoelectronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/136204. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).