Multi-level signaling in memory with wide system interface

Patent metadata

Field	Value
Publication number	US-11233681-B2
Application number	US-202016866191-A
Country	US
Kind code	B2
Filing date	May 4, 2020
Priority date	Aug 7, 2017
Publication date	Jan 25, 2022
Grant date	Jan 25, 2022

Abstract

Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

First claim

What is claimed is:

1. An apparatus, comprising:
an array of memory cells;
a controller configured to control operation of memory cells in the array of memory cells;
an interposer formed of a first material and operatively coupled with the array of memory cells and the controller, wherein the interposer comprises a first plurality of channels between the array of memory cells and the controller, and wherein the first material comprises silicon;
a substrate coupled with the interposer and the controller, the substrate formed of a second material, wherein the interposer further comprises a second plurality of channels between the controller and the substrate;
a signaling interface coupled with the array of memory cells and configured to generate a signal modulated using a first modulation scheme based at least in part on a logic state read from the array of memory cells; and
a receiver configured to determine the logic state represented by the signal modulated using the first modulation scheme communicated across at least one channel of the first plurality of channels of the interposer.

2. The apparatus of claim 1 , further comprising:
a driver configured to generate the signal to be transmitted across the at least one channel of the first plurality of channels of the interposer based at least in part on a plurality of information bits.

3. The apparatus of claim 1 , wherein the second material comprises silicon, germanium, gallium arsenide, gallium nitride, or any combination thereof.

4. The apparatus of claim 1 , wherein the first material and the second material comprise a same material.

5. The apparatus of claim 1 , wherein:
the signal communicated across the at least one channel of the first plurality of channels of the interposer comprises a multi-level signal; and
the at least one channel of the first plurality of channels of the interposer comprises a unidirectional channel.

6. The apparatus of claim 1 , wherein the signal comprises a binary-level signal.

7. The apparatus of claim 6 , wherein the first modulation scheme comprises a non-return-to-zero (NRZ) scheme, a unipolar encoding scheme, a bipolar encoding scheme, a Manchester encoding scheme, a two-level pulse amplitude modulation (PAM) scheme, or a combination thereof.

8. The apparatus of claim 1 , wherein the signal comprises a non-binary signal.

9. The apparatus of claim 8 , wherein the first modulation scheme comprises a four-level pulse amplitude modulation (PAM) scheme, an eight-level PAM scheme, a quadrature amplitude modulation (QAM) scheme, quadrature phase shift keying, or a combination thereof.

10. The apparatus of claim 1 , wherein the array of memory cells transmits the signal across a subset of the first plurality of channels of the interposer to the controller.

11. A method, comprising:
identifying, by a controller of a memory device, information to be written to an array of memory cells;
generating, by the controller at a signaling interface based at least in part on a logic state read from the array of memory cells, a signal that represents a plurality of bits of the identified information, wherein the signal is modulated using a first modulation scheme; and
transmitting, by the controller, the signal to the array of memory cells across an interposer that comprises a first plurality of channels between the array of memory cells and the controller and a second plurality of channels between the controller and a substrate, wherein the interposer is formed of a first material and coupled with the substrate, and wherein the substrate is formed of a second material, and wherein the first material comprises silicon.

12. The method of claim 11 , wherein the second material comprises silicon, germanium, gallium arsenide, gallium nitride, or any combination thereof.

13. The method of claim 11 , wherein the first material and the second material comprise a same material.

14. The method of claim 11 , further comprising:
comparing, by the array of memory cells, the signal to one or more voltage thresholds;
identifying, by the array of memory cells, the plurality of bits represented by the signal based at least in part on comparing the signal to the one or more voltage thresholds; and
writing, by the array of memory cells, the plurality of bits represented by the signal to one or more memory cells of the array of memory cells.

15. An apparatus, comprising:
an array of memory cells;
an interposer formed of a first material and operatively coupled with the array of memory cells, wherein the interposer comprises a first plurality of channels, and wherein the first material comprises silicon;
a substrate coupled with the interposer and a controller, the substrate formed of a second material, wherein the interposer further comprises a second plurality of channels between the controller and the substrate;
a signaling interface coupled with the array of memory cells; and
the controller operatively coupled with the interposer, the controller configured to:
identify information to be written to the array of memory cells;
generate, at the signaling interface, a signal that represents a plurality of bits of the identified information, wherein the signal is modulated using a first modulation scheme; and
transmit the signal to the array of memory cells across the interposer.

16. The apparatus of claim 15 , wherein the second material comprises silicon, germanium, gallium arsenide, gallium nitride, or any combination thereof.

17. The apparatus of claim 15 , wherein the first material and the second material comprise a same material.

18. The apparatus of claim 15 , wherein the controller is further configured to:
compare the signal to one or more voltage thresholds;
identify the plurality of bits represented by the signal based at least in part on comparing the signal to the one or more voltage thresholds; and
write the plurality of bits represented by the signal to one or more memory cells of the array of memory cells.

19. The apparatus of claim 15 , wherein:
the signal comprises a binary-level signal; and
the first modulation scheme comprises a non-return-to-zero (NRZ) scheme, a unipolar encoding scheme, a bipolar encoding scheme, a Manchester encoding scheme, a two-level pulse amplitude modulation (PAM) scheme, or a combination thereof.

20. The apparatus of claim 15 , wherein:
the signal comprises a non-binary signal; and
the first modulation scheme comprises a four-level pulse amplitude modulation (PAM) scheme, an eight-level PAM scheme, a quadrature amplitude modulation (QAM) scheme, quadrature phase shift keying, or a combination thereof.

Assignees

• Micron Technology Inc

Inventors

• Hollis Timothy M
• Balb Markus
• Ebert Ralf

Classifications

• G11C7/1003

  Interface circuits for daisy chain or ring bus memory arrangements · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title

• G11C11/565

  using capacitive charge storage elements · CPC title

• G11C11/56 Primary

  using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title