High-speed ethernet coding

Patent metadata

Field	Value
Publication number	US-11233603-B2
Application number	US-202016888538-A
Country	US
Kind code	B2
Filing date	May 29, 2020
Priority date	Mar 9, 2015
Publication date	Jan 25, 2022
Grant date	Jan 25, 2022

Abstract

A BASE-T Ethernet transceiver is disclosed. The transceiver includes a BASE-T Ethernet transmit circuit that employs a data framing module. The data framing module includes an input interface to receive Ethernet block data bits, and, forward error correction encoder is coupled to the logic to encode at least a first portion of the data bits to generate first error check bits. A Reed-Solomon (RS) encoder is coupled to the logic to encode at least a second portion of the data bits in accordance with a Reed-Solomon error code to generate second error check bits. A symbol mapper modulates the Ethernet block data bits in accordance with an SQ64 constellation comprising back-to-back PAM8 symbols.

First claim

What is claimed is:

1. A BASE-T Ethernet transceiver comprising:
a BASE-T Ethernet transmit circuit including
a BASE-T Ethernet data framing circuitry including
an input interface configured to receive an Ethernet block of data bits for transmission over an Ethernet interface to a receiver,
forward error correction (FEC) encoder circuitry coupled to the input interface and configured to encode the Ethernet block of data bits to generate error correction information for use by the receiver to correct errors in a received Ethernet block of bits; and
a symbol mapper configured to modulate the Ethernet block of data bits and the error correction information into multiple back-to-back PAM8 symbols in accordance with a 64SQ symbol constellation, the 64SQ constellation forming a square grid of sixty-four constellation points.

2. The BASE-T Ethernet transceiver of claim 1 , wherein the FEC encoder circuitry comprises a Low Density Parity Check (LDPC) encoder coupled to the input interface to encode a first portion of the Ethernet block of data bits to generate error correction information defined by error check bits.

3. The BASE-T Ethernet transceiver of claim 2 , further comprising a Reed-Solomon encoder coupled to the input interface to encode a second portion of the data bits other than the first portion in accordance with a Reed-Solomon error correction code.

4. The BASE-T Ethernet transceiver of claim 3 , wherein the Reed-Solomon error correction code comprises an RS256 (128, 110) error code.

5. The BASE-T Ethernet transceiver of claim 3 , wherein the BASE-T Ethernet transmit circuit further comprises:
a transmitter to transmit the back-to-back PAM8 symbols at a symbol rate within the range of 500 MS/s-505 MS/s.

6. The BASE-T Ethernet transceiver of claim 1 , wherein the first portion of the data bits comprise least-significant bits (LSBs) of the Ethernet block data bits.

7. The BASE-T Ethernet transceiver of claim 1 , wherein the second portion of the data bits other than the first portion comprise most-significant bits (MSBs) of the Ethernet block data bits.

8. A method of transferring Ethernet data, the method comprising:
framing BASE-T Ethernet data including
receiving an Ethernet block of data bits for transmission over an Ethernet interface to a receiver,
encoding the Ethernet block of data bits in accordance with a forward error correction (FEC) code to generate error correction information for use by the receiver to correct errors in a received Ethernet block of bits; and

modulating the Ethernet block of data bits and the error correction information into multiple back-to-back PAM8 symbols in accordance with a 64SQ symbol constellation, the 64SQ constellation forming a square grid of sixty-four constellation points.

9. The method according to claim 8 , wherein encoding the first portion of the data bits in accordance with an FEC code comprises:
encoding a first portion of the Ethernet block of data bits in accordance with a Low Density Parity Check (LDPC) code to generate error correction information defined by error check bits.

10. The method according to claim 8 , further comprising:
encoding a second portion of the data bits other than the first portion via a Reed-Solomon error correction code.

11. The method according to claim 10 , wherein the encoding of the second portion of the data bits comprises:
encoding the second portion of the data bits via an RS256 (128, 110) error code.

12. The method according to claim 10 , wherein the encoding of the second portion of the data bits other than the first portion comprises:
encoding most-significant bits (MSBs) of the Ethernet block data bits.

13. The method according to claim 8 , wherein the modulating further comprises:
generating each PAM8 symbol as a set of coset partitioned bits having unique least-significant bits (LSBs) and a most-significant bit (MSB) shared by multiple sets of coset partitioned bits.

14. The method according to claim 13 , wherein the generating each PAM8 symbol as a set of coset partitioned bits comprises:
generating each PAM8 symbol as a set of coset partitioned bits having unique least-significant bits (LSBs) and a most-significant bit (MSB) shared by multiple sets of coset partitioned bits.

15. The method according to claim 8 , wherein the modulating further comprises:
generating each PAM8 symbol as a set of Gray coded bits.

16. The method according to claim 8 , further comprising:
transmitting the PAM8 symbols at a symbol rate within the range of 500 MS/s-505 MS/s.

17. The method according to claim 8 , wherein encoding the first portion of the data bits in accordance with a forward error correction (FEC) code to generate error information comprises:
encoding least-significant bits (LSBs) of the Ethernet block data bits.

Assignees

• Marvell Asia Pte Ltd

Inventors

• Farjadrad Ramin
• Langner Paul

Classifications

• H03M13/255

  with Low Density Parity Check [LDPC] codes · CPC title

• H04L1/0041 Primary

  Arrangements at the transmitter end · CPC title

• H03M13/1102

  Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes · CPC title

• H04L27/04

  Modulator circuits; Transmitter circuits · CPC title

• H03M13/1515

  Reed-Solomon codes · CPC title