High-speed successive approximation analog-to-digital converter with improved mismatch tolerance

Patent metadata

Field	Value
Publication number	US-11233522-B2
Application number	US-202016948790-A
Country	US
Kind code	B2
Filing date	Oct 1, 2020
Priority date	May 28, 2020
Publication date	Jan 25, 2022
Grant date	Jan 25, 2022

Abstract

An image sensor may contain an array of imaging pixels. Each pixel column outputs signals that are read out using a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include at least first and second input sampling capacitors, a comparator, a capacitive digital-to-analog converter (CDAC), and associated control circuitry. If desired, the SAR ADC may include a bank of more than two input sampling capacitors alternating between sampling and conversion. The first capacitor may be used to sample an input signal while conversion for the second capacitor is taking place. Prior to conversion, an input voltage of the comparator and an output voltage of the CDAC may be initialized. During conversion of the signal on the first capacitor, the first capacitor is embedded within the SAR ADC feedback loop to prevent charge sharing between the input sampling capacitor and the CDAC, thereby mitigating potential capacitor mismatch issues.

First claim

What is claimed is:

1. An image sensor, comprising:
a plurality of image sensor pixels; and
an analog-to-digital converter (ADC) circuit having an input configured to receive an input signal from the plurality of image sensor pixels, wherein the ADC circuit comprises:
a first input sampling capacitor;
a second input sampling capacitor;
a comparator having an input that is selectively coupled to the first and second input sampling capacitors; and
a digital-to-analog converter (DAC) circuit having a plurality of capacitors and an output on which a digital-to-analog converter (DAC) voltage is generated, wherein the first input sampling capacitor is coupled in series between the output of the DAC circuit and the input of the comparator during conversion, and wherein the second input sampling capacitor is used to sample another input signal while the first input sampling capacitor is coupled in series between the output of the DAC circuit and the input of the comparator during the conversion.

2. The image sensor of claim 1 , wherein the comparator is configured to receive a comparator supply voltage, and wherein the input signal has a common-mode voltage that is greater than the comparator supply voltage.

3. The image sensor of claim 1 , wherein the comparator is configured to receive a comparator supply voltage, and wherein the plurality of capacitors of the DAC circuit is precharged using a level-shifted voltage that is greater than the comparator supply voltage.

4. The image sensor of claim 3 , wherein the input signal has a common-mode voltage that is dithered to increase a signal-to-noise of the ADC circuit by dithering the level-shifted voltage.

5. The image sensor of claim 1 , wherein the ADC circuit further comprises:
an autozero switch connected to the comparator, wherein the first input sampling capacitor is selectively shorted to the input of the comparator while the autozero switch is turned on.

6. The image sensor of claim 5 , wherein the second input sampling capacitor is discharged while the first input sampling capacitor is selectively shorted to the input of the comparator.

7. The image sensor of claim 1 , wherein the ADC circuit further comprises:
a first switch coupled between the first input sampling capacitor and the input of the ADC circuit; and
a second switch coupled between the first input sampling capacitor and the input of the comparator, wherein the second switch is turned off before the first switch is turned off to prevent signal dependent charge injection from the first switch.

8. The image sensor of claim 1 , wherein the ADC circuit is further configured to inject a midscale voltage onto the DAC circuit prior to the conversion.

9. The image sensor of claim 8 , wherein the input of the comparator is initialized to a first predetermined voltage that is a function of a comparator offset voltage prior to the conversion.

10. The image sensor of claim 9 , wherein the output of the DAC circuit is initialized to a second predetermined voltage that is a function of the midscale voltage and a level-shifted voltage that is used to precharge the plurality of capacitors of the DAC circuit prior to the conversion.

11. The image sensor of claim 10 , wherein the first and second predetermined voltages are independent of the input signal received at the input of the ADC circuit.

12. The image sensor of claim 1 , wherein a voltage level at the input of the comparator is displaced by a voltage that is a function of the input signal during the conversion, and wherein a feedback loop of the ADC circuit is configured to counteract the voltage displacement at the input of the comparator during the conversion.

13. A method of operating an image sensor having a plurality of pixels and an analog-to-digital converter (ADC) circuit, the method comprising:
using the plurality of pixels to image a scene;
using the ADC circuit to receive an input signal from the plurality of pixels;
with a first sampling capacitor in the ADC circuit, sampling the input signal;
with a capacitive digital-to-analog converter (CDAC) circuit in the ADC circuit, generating an output voltage; and
preventing charge sharing between the first input sampling capacitor and a plurality of capacitors in the CDAC circuit by embedding the first sampling capacitor within a feedback loop of the ADC circuit.

14. The method of claim 13 , further comprising:
using the CDAC circuit to convert a signal on a second sampling capacitor in the ADC circuit while the first sampling capacitor is sampling the input signal.

15. The method of claim 14 , further comprising:
performing autozeroing on a comparator in the ADC circuit;
while autozeroing the comparator, discharging the second sampling capacitor and precharging the plurality of capacitors in the CDAC circuit using a level-shifted voltage.

16. The method of claim 15 , further comprising:
dithering the level-shifted voltage to reduce quantization noise for the ADC circuit.

17. The method of claim 15 , further comprising:
using a first switch to couple the first sampling capacitor to the plurality of pixels;
using a second switch to couple the first sampling capacitor to the comparator; and
preventing signal dependent charge injection of the first switch by turning off the second switch before turning off the first switch.

18. The method of claim 15 , further comprising:
initializing the output voltage of the CDAC circuit prior to converting the input signal; and
initializing an input of the comparator prior to converting the input signal.

19. The method of claim 18 , wherein embedding the first sampling capacitor within the feedback loop of the ADC circuit introduces a voltage differential at the input of the comparator, and wherein the feedback loop of the ADC circuit nullifies the voltage differential when converting the input signal.

20. An analog-to-digital converter, comprising:
a first input sampling capacitor;
a second input sampling capacitor;
a comparator selectively coupled to the first and second input sampling capacitors; and
a digital-to-analog converter (DAC) selectively coupled to the first and second input sampling capacitors, wherein the DAC comprises a plurality of capacitors, and wherein charge sharing between the first input sampling capacitor and the plurality of capacitors in the DAC is prevented to mitigate the effects of mismatch between the first and second input sampling capacitors.

21. The analog-to-digital converter of claim 20 , wherein the first input sampling capacitor is selectively coupled between an output of the digital-to-analog converter and an input of the comparator.

22. The analog-to-digital converter of claim 20 , wherein the charge sharing between the first input sampling capacitor and the plurality of capacitors in the DAC is prevented by embedding the first input sampling capacitor within a feedback loop of the analog-to-digital converter.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Mudegowdar Ishwar Chandra
• Pankrac Tomas

Classifications

• H03M1/466

  using switched capacitors · CPC title

• H03M1/201

  by dithering · CPC title

• H03M1/0607 Primary

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/001

  Analogue/digital/analogue conversion · CPC title