Gain calibration device and method for residue amplifier of pipeline analog to digital converter

Patent metadata

Field	Value
Publication number	US-10826516-B2
Application number	US-201916504380-A
Country	US
Kind code	B2
Filing date	Jul 8, 2019
Priority date	Oct 26, 2018
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

A gain calibration device for an ADC residue amplifier includes a DAC and a flash ADC. The DAC is configured to convert the digital signal to an analog signal, and the DAC includes a calibration module used in the gain calibration of the ADC residual amplifier. The flash ADC is configured to generate a digital signal, the flash ADC includes a plurality of comparators, the total number of the plurality of comparators is equal to the number of output bits of the flash ADC, and the comparators are configured to be unevenly distributed in an input range.

First claim

What is claimed is:

1. A gain calibration device for an analog to digital converter (ADC) residual amplifier, the gain calibration device comprising:
a digital to analog converter (DAC) configured to convert a digital signal to an analog signal, wherein the DAC includes a calibration module used in a gain calibration of the ADC residue amplifier; and
a flash analog to digital converter (ADC) configured to generate the digital signal and including a plurality of comparators,
wherein a number of the plurality of comparators is equal to a number of output bits of the flash ADC, and wherein the plurality of comparators provides a plurality of threshold voltages that are unevenly distributed in an input range,
wherein the input range includes a zero point voltage of the input signal.

2. The gain calibration device according to claim 1 , wherein the flash ADC is configured to generate the digital signal by digitally converting a sampling signal of an input signal.

3. The gain calibration device according to claim 2 , further including a part of a stage of a pipeline analog-digital converter (ADC), wherein the pipeline ADC includes the ADC residue amplifier configured to amplify a residue signal.

4. The gain calibration device according to claim 3 , wherein the residue signal is generated by subtracting the analog signal from the sampling signal of the input signal.

5. The gain calibration device according to claim 1 , wherein the DAC includes a multiply digital to analog converter, wherein the calibration module includes a calibration capacitor configured to be charged with a reference voltage in a calibration interval.

6. The gain calibration device according to claim 5 , wherein the calibration capacitor is configured to be charged to an electric potential equal to ½ of the input range, and wherein the threshold voltages provided by the uneven comparator is set to avoid a negative effect of a calibration signal in a dynamic range of the residue amplifier.

7. The gain calibration device according to claim 1 , wherein the gain calibration of the ADC residue amplifier includes a background calibration, and wherein the background calibration is performed by inputting a calibration signal to the DAC.

8. The gain calibration device according to claim 7 , wherein the input of the calibration signal is controlled by a pseudo-random noise sequence.

9. The gain calibration device according to claim 8 , wherein an input of the calibration signal is allowed when amplitude of the input signal is located in the input range.

10. A gain calibration method for an analog to digital converter (ADC) residue amplifier, comprising:
configuring a flash analog to digital converter (ADC) to generate a digital signal, wherein the flash ADC includes a plurality of comparators, and a number of the plurality of comparators is equal to a number of output bits of the flash ADC;
configuring the plurality of comparators to provide a plurality of threshold voltages in an input range, wherein the plurality of comparators provides the plurality of threshold voltages that are unevenly distributed in the input range;
configuring a digital to analog converter (DAC) to convert the digital signal to an analog signal; and
configuring a calibration module of the DAC to perform a gain calibration for the ADC residue amplifier, wherein the input range includes a zero point voltage of the input signal.

11. The gain calibration method according to claim 10 , wherein the flash ADC is configured to generate the digital signal by digitally converting a sampling signal of an input signal.

12. The gain calibration method according to claim 11 , further including a part of a stage of a pipeline analog-digital converter (ADC), wherein the pipeline ADC includes the ADC residue amplifier configured to amplify a residue signal.

13. The gain calibration method according to claim 12 , wherein the residue signal is generated by subtracting the analog signal from the sampling signal of the input signal.

14. The gain calibration method according to claim 10 , wherein the DAC includes a multiply digital to analog converter, and wherein the calibration module includes a calibration capacitor configured to be charged with a reference voltage in a calibration interval.

15. The gain calibration method according to claim 14 , wherein the calibration capacitor is configured to be charged to an electric potential equal to ½ of the input range, and wherein the threshold voltages provided by the uneven comparator is set to avoid a negative effect of a calibration signal in a dynamic range of the residue amplifier.

16. The gain calibration method according to claim 10 , wherein the gain calibration of the ADC residue amplifier includes a background calibration, and wherein the background calibration is performed by inputting a calibration signal to the DAC.

17. The gain calibration method according to claim 16 , wherein the input of the calibration signal is controlled by a pseudo-random noise sequence.

18. The gain calibration method according to claim 16 , wherein an input of the calibration signal is allowed when amplitude of the input signal is within the input range.

Assignees

• Realtek Semiconductor Corp

Inventors

• Lee Chi-Ying

Classifications

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/361

  having a separate comparator and reference value for each quantisation level, i.e. full flash converter type · CPC title

• H03M1/0695

  using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type · CPC title

• H03M1/00

  Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00) · CPC title

• H03M1/1009

  Calibration · CPC title