Digital frequency synthesizer with robust injection locked divider

Patent metadata

Field	Value
Publication number	US-11233520-B2
Application number	US-202017073181-A
Country	US
Kind code	B2
Filing date	Oct 16, 2020
Priority date	Feb 21, 2017
Publication date	Jan 25, 2022
Grant date	Jan 25, 2022

Abstract

A phased-locked loop (PLL) circuit with an injection locked digital digitally controlled oscillator (ILD) that has an ILD control input element, an ILD injection input element and an ILD output element. The PLL circuit also includes an adaptive control unit (ACU), wherein the ACU is configured to receive an error signal and is configured to output an ILD control word. The ILD control input element is configured to receive the ILD control word, and the ILD control word may set a natural oscillation frequency of the ILD. The ILD is further configured to output a first output signal from the ILD output element, where the natural oscillation frequency may set a frequency of the first output signal.

First claim

The invention claimed is:

1. A phased-locked loop (PLL) circuit comprising:
an injection locked digital digitally controlled oscillator (ILD) with an ILD control input element, an ILD injection input element and an ILD output element; and
an adaptive control unit (ACU), wherein the ACU is configured to:
receive an error signal,
output a digitally controlled oscillator (DCO) control signal,
output an ILD control word wherein:
the ILD control input element is configured to receive the ILD control word, wherein the ILD control word is configured to set a natural oscillation frequency of the ILD, and
the ILD is configured to output a first output signal from the ILD output element, wherein the natural oscillation frequency is configured to set a frequency of the first output signal; and

wherein the ILD control word and the DCO control signal comprise a first modulation input signal.

2. The PLL circuit of claim 1 , further comprising a digital loop filter (DLF) wherein the DLF is configured to:
receive the error signal, and
output a filtered error signal to the ACU.

3. The PLL circuit of claim 2 , wherein the ACU is further configured to receive the first modulation input signal.

4. The PLL circuit of claim 3 , wherein the error signal comprises the first output signal.

5. The PLL circuit of claim 4 , further comprising a DCO, wherein the ILD is configured to tune the natural oscillation frequency of the ILD to track a second output signal from the DCO.

6. The PLL circuit of claim 1 , wherein:
the DCO includes a DCO input element and a DCO output element,
the DCO input element is configured to receive the DCO control signal,
the DCO is configured to:
output the second output signal at the DCO output element; and
set a frequency of the second output signal based on the DCO control signal received by the DCO input element,

the ILD injection input element is configured to receive the second output signal from the DCO output element, and
the ILD is configured to synchronize a phase of the first output signal from the ILD output element to a phase of the second output signal from the DCO output element.

7. The PLL circuit of claim 6 , further comprising a time to digital converter (TDC), which includes a TDC output element, a first TDC input element and a second TDC input element, wherein:
the TDC is configured to output the error signal at the TDC output element,
the first TDC input element is configured to receive a reference frequency input signal, and
the second TDC input is configured to receive a loop feedback signal, wherein the loop feedback signal comprises the first output signal from the ILD output.

8. The PLL circuit of claim 7 , wherein a PLL output element is the DCO output element and the phase of the second output signal from the DCO output element is synchronized with a phase of the reference frequency input signal.

9. The PLL circuit of claim 5 , further comprising a multi-modulus divider (MMD), including an MMD control input element, an MMD injection input element, and an MMD output element and wherein:
the MMD control input element is configured to receive an MMD control signal comprising the sum of a second modulation input and a frequency control word (FCW),
the MMD injection input element is configured to receive the first output signal from the ILD output element, and
the MMD is configured to output a loop feedback signal, and wherein the MMD is configured to set the frequency of the loop feedback signal based on the MMD control signal.

10. The PLL circuit of claim 9 , further comprising a delta-sigma (DS) unit, wherein the DS unit is configured to:
receive the sum of:
the second modulation input; and
the FCW; and

output the MMD control signal to the MMD control input element.

11. The PLL circuit of claim 10 , wherein the first modulation input is equal to an inverse polarity of the second modulation input.

12. A method comprising switching a phased locked loop (PLL) to calibration mode, wherein calibration mode comprises:
isolating a main oscillator from the PLL;
switching a control input element of an injection locked digitally controlled oscillator (ILD) of the PLL to receive a first input control word, wherein the ILD comprises the ILD control input element, an ILD injection input element and an ILD output element;
operating the PLL with the ILD as a PLL oscillator;
outputting, by the ILD, a first output signal from the ILD output element;
receiving, by a digital loop filter (DLF), an error signal;
outputting, by the DLF, a filtered error signal;
receiving, by an adaptive control unit (ACU) of the PLL, as input: the error signal, the filtered error signal and a first modulation input signal,
outputting, by the ACU, an ILD control word to the ILD control element, wherein:
the ILD control word is configured to be determined based on the filtered error signal, the error signal and the first modulation input signal,
the ILD control word is configured to set a natural oscillation frequency of the ILD, and
the natural oscillation frequency is configured to set a frequency of the first output signal from the ILD; and
estimating, by the ACU, a calibration value, wherein the calibration value correlates the first modulation input signal to a second modulation input signal.

13. The method of claim 12 , wherein the ACU estimates the calibration value by means of adaptive filtering, wherein adaptive filtering comprises one or more of Kalman filtering, recursive least squares (RLS), and least mean squares (LMS).

14. The method of claim 12 , further comprising switching the PLL to operating mode, wherein operating mode comprises:
switching the control input of the ILD of the PLL to receive a second input control signal, wherein the second input control signal comprises the first modulation input scaled by the calibration value;
setting a control input of the main oscillator to receive the first input control signal;
connecting the output signal of the main oscillator to an injection input element of the ILD; and
operating the PLL with the main oscillator acting as the PLL oscillator.

15. A phased-locked loop (PLL) circuit comprising:
an injection locked digital digitally controlled oscillator (ILD) with an ILD control input element, an ILD injection input element and an ILD output element;
an adaptive control unit (ACU), wherein the ACU is configured to:
receive an error signal;
output an ILD control word wherein:
the ILD control input element is configured to receive the ILD control word, wherein the ILD control word is configured to set a natural oscillation frequency of the ILD, and
the ILD is configured to output a first output signal from the ILD output element, wherein the natural oscillation frequency is configured to set a frequency of the first output signal; and

a digital loop filter (DLF) wherein the DLF is configured to:
receive the error signal, and
output a filtered error signal to the ACU, and

wherein the PLL is configured to operate in a calibration mode, wherein while in calibration mode the ACU is configured to determine the ILD control word based on the filtered error signal, the error signal and a first modulation input signal.

16. The PLL circuit of claim 15 , further comprising a digitally controlled oscillator (DCO),
wherein the ILD is configured to tune the natural oscillation frequency of the ILD to track a second output signal from the DCO, and
wherein the ACU is configured to output a DCO control signal.

17. The PLL circuit of claim 16 , wherein:
the

Assignees

• Infineon Technologies Ag
• Milano Politecnico

Inventors

• Cherniak Dmytro
• Levantino Salvatore
• Tiebout Marc
• Nonis Roberto

Classifications

• H03B5/1228

  the amplifier comprising one or more field effect transistors · CPC title

• H03B5/124

  the means comprising a voltage dependent capacitance · CPC title

• H03L7/197

  a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division {(H03L7/1806 takes precedence)} · CPC title

• H03B2201/0208

  the means being an element with a variable capacitance, e.g. capacitance diode · CPC title

• H03L7/24 Primary

  using a reference signal directly applied to the generator · CPC title